Folded FIFO Memory Generator for Unused Cell Optimization
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Solution Overview
Problem
Conventional FIFO memory implementations lead to inefficiencies due to mismatched physical characteristics, resulting in unused memory cells and increased power consumption and space requirements.
Innovation Solution
The method involves folding the depth and width of the FIFO memory to identify corresponding memory element dimensions, allowing for efficient storage by using a memory element with different dimensions than the FIFO, such as a 128×1 FIFO being implemented as a 16×8 memory element, where each row stores 8 bits, thereby utilizing all storage locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 128×1 FIFO is implemented using RAM with 8-bit wide rows, then the FIFO can store 128 entries, but 7 bits of each row remain unused leading to wasted space and power consumption
Solution Approach 1:
The patent changes the dimensional parameters of the memory structure by folding the FIFO into a three-dimensional array configuration. Instead of using a conventional 2D memory array with wasted space, the invention reorganizes the storage into multiple banks with specific depth, width, and height parameters that precisely match the FIFO requirements, eliminating unused memory cells and optimizing power consumption.
2Quantity of substance
If a 128×1 FIFO is implemented using RAM with 8-bit wide rows, then the FIFO can store 128 entries, but the hardware system requires more space than necessary
Solution Approach 1:
The patent transforms the memory dimensional parameters by creating a folded structure with specific depth, width, and height values. This reconfiguration allows the memory to achieve the required 128-entry capacity while minimizing the physical area by eliminating unused memory cells that would exist in a conventional flat memory arrangement.
Solution Approach 2:
The patent introduces a third dimension to the memory structure by organizing the FIFO into a three-dimensional array with depth, width, and height parameters. This dimensional transformation allows efficient packing of storage elements and eliminates the wasted space inherent in two-dimensional memory arrangements, thereby reducing the overall hardware area.
3Adaptability or versatility
If conventional generators produce synthesizable code for FIFO memories, then different FIFO variations can be generated, but physical characteristics lead to inefficiencies with unused memory cells
Solution Approach 1:
The patent modifies the memory dimensional parameters by implementing a folded structure with configurable depth, width, and height. This allows the generation of different FIFO variations with optimized parameters that eliminate unused memory cells, thereby reducing power consumption while maintaining the ability to produce various FIFO configurations through synthesizable code.
4Adaptability or versatility
If conventional generators produce synthesizable code for FIFO memories, then different FIFO variations can be generated, but the hardware system requires more area than necessary
Solution Approach 1:
The patent optimizes the memory dimensional parameters by folding the FIFO into a three-dimensional structure with specific depth, width, and height values. This allows the generation of different FIFO variations while minimizing the hardware area by eliminating unused memory cells that would be present in conventional implementations.
Solution Approach 2:
The patent applies dimensional transformation by organizing the FIFO memory into a three-dimensional array structure. This dimensional change enables efficient space utilization and reduces the overall hardware area while maintaining the capability to generate various FIFO configurations through parameter adjustment.
Data Source
AI summary
Synthesizable code representing first-in-first out (FIFO) memories may be used to produce FIFO memories in a hardware element or system. To more efficiently use a memory element that stores the data in a FIFO, a code generator may generate a wrapper that enables the FIFO to use a memory element with different dimension (i.e., depth and width) than the FIFO's dimensions. For example, the wrapper enables a 128 deep, 1 bit wide FIFO to store data in a memory element with 16 rows that store 8 bits each. To any system communicating with the FIFO, the FIFO behaves like a 128×1 FIFO even though the FIFO is implemented using a 16×8 memory element. To do so, the code generator may generate a wrapper which enables the folded memory element to behave like a memory element that was not folded.