3D Package Configuration Using Folded Flexible Circuit Board
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Solution Overview
Problem
Current 3D package configurations are complex, time-consuming, and costly due to processes like thin film deposition and photolithography, with low yield rates, necessitating a simpler and more efficient manufacturing method.
Innovation Solution
A 3D package configuration using a lead frame with vertically stacked semiconductor package units, where each unit comprises a semiconductor die and a folded flexible circuit board with insulating substrate and conductive layers, allowing for electrical connections through bonding pads and conductive holes, enabling sequential stacking and connection without the need for advanced semiconductor manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D package configurations use thin film deposition, photolithography, and etching processes, then electrical connections between stacked dies can be achieved, but the manufacturing process becomes complicated and time-consuming with low yield rates and high costs
Solution Approach 1:
The patent extracts and eliminates the complex semiconductor manufacturing processes (thin film deposition, photolithography, etching) from the 3D packaging workflow. Instead of using these advanced processes to create interconnect structures within the semiconductor layers, the invention uses conventional wire bonding or flip chip bonding techniques that connect the stacked dies to a substrate through simpler, more established processes, thereby reducing manufacturing complexity while maintaining electrical connection reliability
Solution Approach 2:
The patent segments the interconnection function into separate components: the stacked semiconductor dies are connected to a substrate through individual bonding processes rather than through integrated complex interconnect structures. This segmentation allows each die to be bonded independently using conventional techniques, simplifying the overall manufacturing process while achieving the same electrical connectivity function
2Manufacturing precision
If advanced semiconductor manufacturing processes are used for 3D packaging, then precise electrical interconnections can be achieved, but the packaging time increases and yield rates decrease
Solution Approach 1:
The patent employs disposable bonding pads and interconnect structures that are created through simple, fast processes rather than through complex, time-consuming manufacturing steps. These interconnect elements are designed to be formed quickly through conventional bonding processes, sacrificing some structural complexity to gain significant improvements in packaging speed and yield rate
3Device complexity
If conventional wire bonding or flip chip bonding is used for electrical connections, then manufacturing costs and process complexity are reduced, but achieving reliable electrical connections between stacked dies becomes more challenging
Solution Approach 1:
The patent applies preliminary bonding pad formation and alignment techniques that ensure reliable electrical connections are established before the actual stacking process. By preparing the bonding surfaces in advance with precise alignment features and pre-formed bonding pads, the invention enables conventional bonding methods to achieve reliability levels previously only attainable through complex manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the manufacturing process, increases yield rates, and reduces costs by using conventional techniques for electrical connections, while maintaining the complexity and efficiency required for high-power semiconductor packages.
Implementation Method 1
the bottom surface of the semiconductor die is bonded to the first surface and electrically connected to the folded flexible circuit board
Implementation Method 2
a circuit formed on a surface of the flexible insulating substrate
Data Source
AI summary
A novel 3D package configuration is provided by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a lead frame and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance.