Folded FRAM Channel Structure for Higher Cell Current Density
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Solution Overview
Problem
The challenge in scaling down Ferroelectric Random Access Memory (FRAM) devices is the requirement for larger cell current, which results in an enlarged footprint due to the horizontal channel layer configuration, making it difficult to maintain memory cell size without increasing layout area.
Innovation Solution
The implementation of a folded channel layer structure within FRAM memory cells, allowing for increased vertical height of the channel layer without expanding the memory cell layout, thereby enhancing cell current without increasing the footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory cell size is reduced for scaling down integrated circuits, then the footprint is reduced, but the cell current decreases
Solution Approach 1:
The patent transitions the channel layer from a planar two-dimensional structure to a three-dimensional folded structure. The channel layer is configured with vertical sides extending from a bottom surface, creating a folded geometry that increases the effective channel length and current-carrying capacity without increasing the lateral footprint of the memory cell. This dimensional transformation allows the channel to utilize vertical space rather than lateral space, resolving the contradiction between small footprint and sufficient cell current.
2Power
If the channel layer height is increased to enhance cell current, then the current capacity improves, but the memory cell footprint expands
Solution Approach 1:
The invention utilizes the vertical dimension by folding the channel layer upward to form vertical sides. This allows the channel length to extend in the vertical direction rather than solely in the lateral direction. The folded configuration increases the effective channel length and current capacity while confining the lateral footprint within the original planar boundaries, thus improving cell current without expanding the memory cell footprint.
Solution Approach 2:
The folded channel layer is nested within the vertical space above the substrate. The channel structure folds back on itself, with portions of the channel occupying vertical space that would otherwise be unused. This nesting approach allows the channel to achieve greater length and current capacity by utilizing the vertical volume within the existing cell footprint, rather than expanding laterally.
Data Source
AI summary
A device includes a word line, a dielectric layer, a gate dielectric layer, a semiconductive layer, a source line, and a memory stack. The word line is over a substrate. The dielectric layer is over the word line and has inner sidewalls over the word line. The gate dielectric layer is in contact with the word line and lines a top surface and inner sidewalls of the dielectric layer. The semiconductive layer is conformally over the gate dielectric layer. The semiconductive layer includes a source portion, a drain portion, and a channel portion. The source portion and the drain portion are over the top surface of the dielectric layer. The channel portion interconnects the source portion and the drain portion and in at a position lower than the source portion. The source line and the memory stack are respectively over the source portion and the drain portion.