Folded-Channel GaN FET Structure for High Breakdown and Low Resistance

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Solution Overview

Problem

Traditional Al(In, Ga)N/GaN field-effect transistors require a long, low-doped N-drift region for high breakdown voltage, leading to increased conduction resistance and device size, which in turn raises manufacturing costs.

Innovation Solution

A folded channel gallium nitride based field-effect transistor with a multi-heterojunction layer and current collapse suppression structure, featuring grooves and stacked layers to increase the drifting region, reduce conduction resistance, and enhance breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the size of the low doped N-drift region is increased to ensure high breakdown voltage, then the breakdown voltage is improved, but the conduction resistance increases sharply

Engineering Contradiction:
Improvebreakdown voltageVSAvoidconduction resistance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a folded channel structure that extends the drift region in the vertical dimension (from source to drain through multiple folds) rather than only in the lateral dimension. This allows the drift region length to be increased for higher breakdown voltage while maintaining a compact lateral footprint, thereby reducing the area and associated manufacturing costs while keeping conduction resistance low through the extended vertical path.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The folded channel structure nests multiple channel segments within a compact lateral space, with each fold containing a portion of the drift region. This nesting allows the drift region to be extended vertically through the structure while maintaining a small overall device area, resolving the contradiction between needing a large drift region for high breakdown voltage and minimizing device area to reduce manufacturing costs.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the size of the low doped N-drift region is increased to ensure high breakdown voltage, then the breakdown voltage is improved, but the area of the device increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The folded channel structure utilizes the vertical dimension to extend the drift region length without proportionally increasing the lateral device area. By folding the channel back and forth in the vertical direction, the patent achieves a long drift region (e.g., 10 micrometers or more) while maintaining a compact lateral footprint, thus resolving the contradiction between high breakdown voltage requirements and device area minimization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different structural configurations to different regions: the folded channel structure is used specifically in the drift region to maximize its length vertically, while other regions of the device maintain standard configurations. This localized application of the folded structure allows the drift region to achieve the necessary length for high breakdown voltage without forcing the entire device area to increase.

Inventive Principle:
Principle #3Local quality

3Reliability

If the size of the low doped N-drift region is increased to ensure high breakdown voltage, then the breakdown voltage is improved, but the manufacturing cost increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

By extending the drift region in the vertical dimension through the folded channel structure, the patent achieves high breakdown voltage without increasing the lateral device area. Since manufacturing cost is closely related to device area (larger wafers require larger device footprints), this vertical extension strategy reduces manufacturing costs while maintaining the necessary breakdown voltage performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the geometric parameters of the drift region by folding it in the vertical direction, transforming a lateral extension problem into a vertical extension problem. This parameter transformation allows the drift region length to be increased (improving breakdown voltage) while the lateral dimensions remain small (reducing manufacturing cost), effectively resolving the contradiction through parameter reconfiguration.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution increases breakdown voltage, reduces conduction resistance, and maintains a compact device size, improving dynamic conduction characteristics and integration efficiency.

Implementation Method 1

an Al (In, Ga) N/GaN heterojunction may spontaneously form two-dimensional electron gas (2DEG) with high concentration and high electron mobility due to strong spontaneous polarization and piezoelectric polarization effects

Methodology Applied
Scientific EffectSpontaneous polarization: Polarisation

Implementation Method 2

an Al (In, Ga) N/GaN heterojunction may spontaneously form two-dimensional electron gas (2DEG) with high concentration and high electron mobility due to strong spontaneous polarization and piezoelectric polarization effects

Methodology Applied
Scientific EffectPiezoelectric polarization: Piezoelectric Effect

Implementation Method 3

the current collapse suppression structure is applicable to provide, when a voltage of a drain electrode is high, a hole injection to the drain electrode, so as to effectively release electrons captured near the drain electrode on a surface of the channel, suppress a current collapse effect

Methodology Applied
Scientific EffectCharge carrier injection:

Data Source

PatentUS12622013B2Folded channel gallium nitride based field-effect transistor and method of manufacturing the same
Publication Date: 2026.05.05 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US12622013B2 patent drawing
  • US12622013B2 patent drawing
  • US12622013B2 patent drawing

AI summary

The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.