Folded-Gate Wide Bandgap Transistor Layout for Thermal Balancing
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Solution Overview
Problem
Conventional field effect transistors face challenges in achieving uniform thermal dissipation and efficient electrical current balancing, leading to increased peak temperatures and reduced manufacturing efficiency due to non-optimal contact finger configurations and wafer via placement.
Innovation Solution
The proposed field effect transistor features an interleaved contact configuration with gate contact fingers distributed between source and drain contact fingers, utilizing through wafer vias to balance current flow and a rectangular shape, which reduces die size and enhances thermal dissipation without increasing peak temperature, suitable for wide bandgap transistors like GaN or SiC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional contact finger configurations are used, then manufacturing is simpler, but thermal dissipation is non-uniform and peak temperature increases
Solution Approach 1:
The gate contact is divided into multiple gate contact fingers that are interleaved with source and drain contact fingers. This segmentation allows heat to be dissipated through multiple distributed contact points across the transistor area, creating a more uniform thermal profile and reducing peak temperature compared to conventional concentrated contact configurations.
Solution Approach 2:
The contact fingers are arranged in an interleaved pattern extending in multiple directions across the transistor area, transforming the thermal dissipation from a one-dimensional or two-dimensional concentrated path to a three-dimensional distributed network. This spatial distribution optimizes heat flow paths and reduces thermal hotspots.
2Temperature
If gate contact fingers are distributed in the transistor area, then thermal dissipation improves, but manufacturing precision requirements increase
Solution Approach 1:
The gate contact fingers are electrically connected to a common gate contact region, merging multiple distributed contact elements into a single electrical entity. This allows the benefits of distributed thermal dissipation to be achieved while maintaining simplified electrical connectivity and reducing the precision requirements for individual finger placement, as they are all tied to the same electrical potential.
3Reliability
If interleaved contact configuration is used, then current balancing improves, but device complexity increases
Solution Approach 1:
The interleaved arrangement of gate contact fingers between source and drain contact fingers creates equipotential regions that facilitate balanced current distribution. The gate contact fingers are held at the same electrical potential and are symmetrically positioned relative to the source and drain contacts, ensuring uniform electric field distribution and balanced current flow across the transistor channel.
Data Source
AI summary
Disclosed in a field effect transistor integrated within an associated transistor area, the field effect transistor comprising a contact configuration with interleaved contact fingers including gate contact fingers having electrically connected gate contact finger sections being distributed in the transistor area and being provided between a source contact finger and a drain contact finger of the contact configuration.