Folded Hadamard Transform Circuits for SATD Block Processing
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Solution Overview
Problem
The existing video encoding technologies face inefficiencies in hardware utilization and computational complexity due to the large transform sizes required for accurate distortion calculation in video encoding, leading to high hardware costs and lower utilization rates, especially when processing larger SATD blocks that exceed the throughput of the prediction stage.
Innovation Solution
The method involves using folded Hadamard transform circuits to split blocks into smaller SATD blocks, allowing shared Hadamard transform circuits to process these blocks in alternating cycles, reducing hardware requirements and increasing utilization rates by buffering temporary results and reusing circuits for both SATD and SAD calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger transform size is used for SATD computation, then coding efficiency is improved, but hardware utilization deteriorates
Solution Approach 1:
The patent divides a large SATD block (e.g., 4×16 or 4×32) into multiple smaller sub-blocks (e.g., four 4×4 blocks) that can be processed independently and in parallel. This segmentation allows the hardware to process multiple regions simultaneously, maintaining high hardware utilization while achieving accurate distortion calculation for large blocks through summation of sub-block results.
Solution Approach 2:
The patent introduces a spatial dimension to the processing by organizing the computation into a two-dimensional array of sub-blocks. Instead of processing one large block sequentially, the hardware processes multiple smaller blocks arranged in a grid, enabling parallel computation across different spatial positions and improving overall throughput.
2Measurement precision
If larger SATD blocks are processed, then compression loss is reduced, but hardware costs increase
Solution Approach 1:
The patent segments a large SATD block into multiple smaller sub-blocks that can be processed by existing hardware circuits. By dividing the computation into manageable pieces, the patent avoids the need for expensive dedicated hardware for large-block processing while maintaining the accuracy benefits of large transform sizes through parallel sub-block processing.
Solution Approach 2:
The patent combines the results from multiple smaller sub-block computations to produce the final SATD value for the large block. This merging approach allows the system to achieve large-block processing capability using smaller, more cost-effective hardware units that process sub-blocks and then aggregate their results.
3Measurement precision
If SATD hardware circuit is designed for processing blocks larger than prediction stage throughput, then coding accuracy is improved, but hardware utilization rate decreases
Solution Approach 1:
The patent segments the large SATD block into multiple sub-blocks that match the prediction stage throughput capability. This allows the hardware to process each sub-block at full utilization while maintaining the overall accuracy of large-block SATD computation by summing the results of all sub-blocks.
Solution Approach 2:
The patent ensures continuous hardware utilization by processing multiple sub-blocks in parallel or in a pipelined manner, eliminating idle time. While one sub-block is being processed, other hardware units work on different sub-blocks, maintaining continuous productive action and maximizing hardware utilization rate.
Data Source
AI summary
Video encoding methods and apparatuses for Sum of Absolute Transformed Difference (SATD) computation by folded Hadamard transform circuits include splitting a current block into SATD blocks, receiving input data associated with a first block of a first SATD block in a first cycle and receiving input data associated with a second block of the first SATD block in a second cycle, and performing calculations for the first block by shared Hadamard transform circuits in the first cycle and performing calculations for the second block by the shared Hadamard transform circuits in the second cycle. Each shared Hadamard transform circuit is a first part of each folded Hadamard transform circuit. The video encoding methods and apparatuses further perform calculations for the entire SATD block by a final part of each folded Hadamard transform circuit to generate a final SATD result of the first SATD block for encoding.