Folded Leadframe for Low Inductance Power Packages
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Solution Overview
Problem
Designing multiple power semiconductor packages that minimize voltage and current losses by reducing interconnect resistance and inductance while maintaining a compact form factor for easy attachment to printed circuit boards, while also being economically viable.
Innovation Solution
A multiple die package design featuring a folded leadframe with parallel plates connected by a belt member, incorporating a second leadframe between the plates, and attaching high side and low side dies, along with an optional integrated circuit, to optimize interconnects and reduce losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple power semiconductor packages are used to reduce interconnect length, then resistance and inductance losses are reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements nesting by placing one leadframe structure inside another, with an inner leadframe containing power semiconductor die and an outer leadframe providing structural support and electrical connections. This nested configuration allows multiple functional elements to be integrated in a compact arrangement, reducing interconnect length and energy losses while managing complexity through hierarchical organization
Solution Approach 2:
The patent combines multiple functions into integrated structures: the leadframe serves simultaneously as structural support, electrical interconnect, and mechanical attachment element. The folded configuration merges the housing and interconnect functions into a single integrated component, reducing the number of separate parts and simplifying manufacturing while maintaining low resistance and inductance pathways
2Loss of energy
If interconnect cross sectional area is maximized to reduce resistance, then voltage losses are reduced, but package volume increases
Solution Approach 1:
The patent transitions from planar interconnect geometry to three-dimensional folded leadframe structures. By folding the leadframe to create parallel plates and vertical connections, the design achieves large effective cross-sectional area for current flow without increasing the package's planar footprint, effectively utilizing the third dimension to reduce resistance while maintaining compact volume
3Loss of energy
If interconnect length is minimized to reduce inductance, then current losses are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates preliminary alignment features directly into the leadframe structure during manufacturing, such as pre-formed attachment surfaces, registration pins, and mechanical interlocks. These features are created in advance during leadframe fabrication, ensuring precise alignment of the power semiconductor die and interconnects before final assembly, thereby reducing inductance while maintaining manufacturability
Data Source
AI summary
A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.