Folded Memory Modules With Configurable Switches

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Solution Overview

Problem

As memory bus speeds increase, maintaining good signal integrity becomes challenging in multi-drop data topologies, where multiple memory devices share data signals, leading to signal degradation and reduced memory speeds.

Innovation Solution

A folded memory module topology is introduced, where each memory module uses only a fraction of the available data lines, reducing loading effects and maintaining signal integrity. This is achieved through configurable memory modules with programmable switches that allow dynamic reconfiguration of data line coupling, enabling efficient data routing and buffering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple memory devices share data signals in a multi-drop topology to expand memory capacity, then memory capacity increases, but signal integrity degrades due to increased loading characteristics

Engineering Contradiction:
Improvememory capacityVSAvoidsignal integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The data bus is segmented into multiple independent folded pairs, where each pair connects to a subset of memory devices. This segmentation reduces the loading on each signal line while maintaining overall memory capacity expansion, as each folded pair operates with reduced loading characteristics compared to a traditional multi-drop topology.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a folded topology that adds a dimensional aspect to the traditional linear multi-drop bus structure. By folding the bus back on itself and creating multiple independent signal paths, the system achieves better signal integrity while maintaining capacity expansion through a structurally different approach.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If memory bus speeds increase to improve performance, then memory speed increases, but maintaining signal integrity becomes increasingly difficult

Engineering Contradiction:
Improvememory bus speedVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

By segmenting the data bus into multiple folded pairs with reduced loading, each signal line can operate at higher speeds without signal integrity degradation. The reduced loading characteristics of each folded pair enable faster signal transitions while maintaining reliability.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If conventional multi-drop topologies are used to expand memory capacity, then memory capacity increases, but data line loading increases reducing memory performance

Engineering Contradiction:
Improvememory capacityVSAvoidmemory performance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The folded topology segments the data lines into multiple independent folded pairs, each connecting to a portion of the total memory capacity. This segmentation allows memory capacity to be expanded while each individual folded pair maintains low loading characteristics, preserving memory performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each folded pair carries only a portion of the total data traffic rather than all memory devices sharing the same lines. This partial action approach reduces the loading on each signal line, maintaining performance while achieving overall capacity expansion through multiple folded pairs.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250103531A1Folded memory modules
Publication Date: 2025.03.27 RAMBUS INC
  • US20250103531A1 patent drawing
  • US20250103531A1 patent drawing
  • US20250103531A1 patent drawing

AI summary

A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.