Folded MOM Capacitor Layout Under On-Chip Inductors
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Solution Overview
Problem
Integrating metal-oxide-metal (MOM) capacitors with inductors and transformers in mobile RF transceivers degrades the performance of the inductors and transformers, and conventional capacitor designs consume significant semiconductor area, reducing available space for active devices.
Innovation Solution
A folded metal-oxide-metal (MOM) capacitor is integrated within the inductor area in the lower back-end-of-line (BEOL) interconnect levels, with multiple sides and a pair of manifolds on the same side, allowing the inductive trace to overlap portions of the capacitor without degrading the inductor's quality factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOM capacitors are integrated with inductors and transformers, then capacitance density is improved, but inductor performance degrades
Solution Approach 1:
The patent transitions from planar capacitor layouts to a three-dimensional folded finger configuration that extends vertically through multiple BEOL interconnect levels. This dimensional change allows the capacitor to occupy the space beneath the inductor, achieving high capacitance density without lateral expansion that would interfere with inductor performance.
Solution Approach 2:
The capacitor structure is nested within the inductor area by placing folded capacitor fingers in lower BEOL interconnect levels while the inductor resides in upper levels. The capacitor fingers are interspersed and folded to fit within the vertical space occupied by the inductor structure, allowing both components to coexist without performance degradation.
2Ease of manufacture
If conventional capacitor designs are used, then manufacturing is simplified, but semiconductor area consumption increases
Solution Approach 1:
The capacitor design utilizes the vertical dimension by extending folded fingers through multiple BEOL interconnect levels (M1-M6). This three-dimensional configuration achieves high capacitance density without requiring additional lateral semiconductor area, as the capacitor fits within the vertical space above the substrate and below the inductor.
Solution Approach 2:
The capacitor is divided into multiple folded finger segments that are distributed across different BEOL interconnect levels. Each finger segment contributes to the total capacitance, and the segmented structure allows efficient space utilization within the available vertical volume, maximizing capacitance per unit area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the formation of high-capacitance density MOM capacitors within the inductor area without affecting the inductor's performance, optimizing semiconductor chip space usage while maintaining high RF performance.
Implementation Method 1
MOM capacitors harness lateral capacitive coupling between plates formed by metallization layers and wiring traces
Implementation Method 2
an inductive trace having one or more turns in one or more different BEOL interconnect levels
Data Source
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AI summary
An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.