Folded Multiplier Layout for Reduced Wiring Delay
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Solution Overview
Problem
Conventional APU architectures for multiplier modules have inefficient layouts, leading to significant wiring path lengths between booth encoders and multiplexers, and between multiplexers and compressor circuitry, which increases layout area, power consumption, and propagation delay.
Innovation Solution
A split or folded multiplier architecture with booth encoder and multiplexer circuitry arranged in a diagonal layout and interleaved with carry-save adder compressor levels, reducing wiring distances and layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multiplier module layout is used, then functional correctness is maintained, but wiring path lengths increase leading to higher propagation delay
Solution Approach 1:
The patent transitions from a conventional linear or grid-based layout to a folded layout where the partial product array is arranged in a folded configuration. This dimensional reorganization allows signals to traverse shorter paths by changing the spatial dimension in which components are arranged, thereby reducing propagation delay while maintaining functional correctness.
Solution Approach 2:
The multiplier module is segmented into distinct functional regions including a first region with initial booth encoders and multiplexers, and a second region with additional components. This segmentation allows for optimized local connections and reduced wiring paths within each region while maintaining overall functional integrity.
2Reliability
If conventional multiplier module layout is used, then functional correctness is maintained, but layout area increases
Solution Approach 1:
By reorganizing the partial product array in a folded layout and arranging booth encoders and multiplexers in specific spatial patterns, the patent reduces the overall footprint area required for the multiplier module while maintaining all necessary functional connections.
Solution Approach 2:
The patent merges adjacent functional blocks and optimizes the placement of booth encoders, multiplexers, and carry-save adders to minimize wasted space. This consolidation reduces the total layout area while preserving functional correctness through careful interconnection design.
3Reliability
If conventional multiplier module layout is used, then functional correctness is maintained, but power consumption increases
Solution Approach 1:
The folded layout reduces the distance that signals and control signals must travel through the circuit. Shorter wiring paths result in lower signal propagation losses and reduced power consumption by the multiplier module while maintaining functional correctness.
Solution Approach 2:
The patent extracts and optimizes the placement of power-intensive components such as carry-save adders and booth encoders to regions where they can operate most efficiently. This strategic positioning reduces overall power consumption by minimizing unnecessary signal travel and optimizing local circuit behavior.
Data Source
AI summary
The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.