Folded Current Sampler Circuit With Mirrored Gain Scaling

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Solution Overview

Problem

Current sampler circuitry faces challenges in achieving optimal performance due to trade-offs between gain and S11 scattering parameter performance, voltage headroom issues, and difficulty in current scaling, particularly in high-resolution applications where parasitic capacitance and bandwidth degradation are concerns.

Innovation Solution

The implementation of a 'folded' sampler circuitry structure using current mirror circuitry, which separates the primary and secondary current paths and employs programmable gain control through cascode transistors, allows for improved S11 performance and reduced stacking, enabling enhanced bandwidth and gain boosting at high frequencies while maintaining low voltage headroom.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional sampler circuitry is used to achieve high gain, then the S11 scattering parameter performance deteriorates

Engineering Contradiction:
ImprovegainVSAvoidS11 scattering parameter performance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The sampler circuitry is divided into separate functional blocks: an input stage receiving the voltage signal, a current mirror circuitry block, and a load circuitry block. This segmentation allows each block to be optimized independently, enabling high gain in the current mirror while maintaining good S11 performance in the input stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The current mirror circuitry acts as an intermediary between the input voltage signal and the load circuitry. It converts the input voltage signal to a current signal and provides gain, isolating the input stage from the load and allowing independent optimization of S11 performance and gain.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If more stacking is used to increase gain, then voltage headroom is reduced

Engineering Contradiction:
ImprovegainVSAvoidvoltage headroom
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

Instead of increasing gain by adding more series stages (vertical stacking), the patent uses a current mirror configuration that provides gain through current multiplication. This approach achieves high gain without increasing the number of stacked devices, thereby preserving voltage headroom.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Power

If bias current is increased to improve current scaling, then bandwidth degradation occurs due to parasitic capacitance

Engineering Contradiction:
Improvecurrent scalingVSAvoidbandwidth
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The current mirror circuitry creates a copy of the input current signal with multiplied amplitude. This copying mechanism provides current scaling without requiring proportional increases in bias current, as the gain is achieved through the mirror ratio rather than raw current magnitude, thereby preserving bandwidth.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in increased secondary current without increasing the bias current, improving bandwidth and S11 parameter, and allows for calibration to compensate for parasitic capacitance effects, thereby enhancing the overall performance and efficiency of the sampler circuitry.

Implementation Method 1

The current mirror circuitry comprises a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path

Methodology Applied
Scientific EffectCurrent mirror effect:

Data Source

PatentUS11431307B2Current signal generation useful for sampling
Publication Date: 2022.08.30 SOCIONEXT INC
  • US11431307B2 patent drawing
  • US11431307B2 patent drawing
  • US11431307B2 patent drawing

AI summary

Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.