Folded Semiconductor Package Substrate Architecture
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Solution Overview
Problem
Semiconductor package miniaturization faces challenges in simplifying interconnects while increasing packaging complexity in smaller form factors, requiring innovative solutions to enhance signal integrity and reduce signal length and resistivity issues.
Innovation Solution
A folded semiconductor package architecture is introduced, featuring a 'virtual recess' created by folding the package substrate, which allows for orthogonal signal paths between embedded and surface-mounted active devices, reducing signal length and improving resistivity through the use of interlayer dielectric layers and electroplated copper pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor package size is reduced for miniaturization, then form factor is improved, but signal integrity deteriorates due to increased resistivity and signal length issues
Solution Approach 1:
The patent introduces a folded substrate architecture that transitions from a planar two-dimensional layout to a three-dimensional folded structure. This dimensional change allows signal paths to fold back on themselves, creating orthogonal routing that reduces the effective signal length and resistivity while maintaining a compact package footprint, thereby resolving the contradiction between miniaturization and signal integrity
Solution Approach 2:
The folded substrate design effectively nests signal paths within the package by folding the substrate back on itself. The signal traces are routed through multiple layers and folds, creating a nested configuration where the signal path is contained within the compact package volume rather than extending outward, thus maintaining signal integrity in a reduced form factor
2Length of stationary object
If package substrate is folded to create orthogonal signal paths, then signal length is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-forming the substrate folds and routing the signal traces through the folded structure before final assembly. The orthogonal signal paths are established during substrate fabrication rather than requiring complex post-assembly routing, which reduces manufacturing complexity despite the folded geometry
Solution Approach 2:
The folded substrate is divided into multiple segments or layers that can be independently fabricated and then assembled. This segmentation allows each layer to be optimized separately and simplifies the manufacturing process by breaking down the complex folded structure into manageable sections that can be produced using standard fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The folded architecture achieves improved signal integrity and reduced signal length, enhancing the performance of semiconductor packages in smaller form factors by creating orthogonal electrical paths and minimizing resistivity issues.
Implementation Method 1
electroplated copper pillars
Implementation Method 2
improving resistivity through the use of interlayer dielectric layers and electroplated copper pillars
Data Source
AI summary
A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.