Folded Sidewall Wiring for Semiconductor Contact Alignment
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Solution Overview
Problem
The sidewall transfer process in semiconductor manufacturing faces challenges in forming contact regions due to the proximity of folded sections to adjacent wiring layers, reducing the margin of deviation in position alignment, and the narrow pitch of wiring layers below the resolution limit, which complicates the closed-loop cut and alignment tolerance.
Innovation Solution
The semiconductor device incorporates a wiring layer with a folded wiring section along the end of a hard mask and a parallel section, using a closed-loop cut in portions except for the folded section, where the folded section and parallel section serve as contact regions for connecting wires, allowing for wider alignment margins and improved tolerance in the closed-loop cut process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the folded section of the sidewall film is used as a contact region, then electrical connection is achieved, but the margin of deviation in position alignment is reduced due to proximity to adjacent wiring layers
Solution Approach 1:
The patent transitions from a two-dimensional planar contact region to a three-dimensional folded structure. The folded section extends vertically along the sidewall, providing additional spatial dimension for contact region placement. This allows the contact region to be positioned away from adjacent wiring layers in the horizontal plane while maintaining electrical connection functionality through the vertical fold.
Solution Approach 2:
The contact region is segmented into distinct functional portions: the folded section providing vertical connection path and the parallel sections providing horizontal access. This segmentation allows independent optimization of each portion - the folded section can be positioned for optimal electrical connection while the parallel sections can be positioned for optimal alignment margin.
2Manufacturing precision
If wiring layers are formed at narrow pitch below the resolution limit, then fine patterning is achieved, but the tolerance of alignment deviation in closed-loop cut is reduced
Solution Approach 1:
The patent utilizes the vertical dimension through the folded sidewall structure to compensate for reduced horizontal alignment tolerance. The folded section provides additional spatial buffer in the vertical direction, allowing larger horizontal deviations without compromising the functionality of the contact region or the integrity of the narrow pitch wiring pattern.
Data Source
AI summary
A semiconductor device comprises a wiring layer. The wiring layer is provided by forming a sidewall film having a closed-loop along a sidewall of a hard mask, etching off the hard mask to leave the sidewall film, and then etching a target material to be etched with a mask of the sidewall film. The wiring layer includes a folded wiring section formed along an end of the hard mask, and a parallel section composed of two parallel wires continued from the folded wiring section. The wiring layer has a closed-loop cut made in a portion except for the folded wiring section and the parallel section. The folded wiring section and the parallel section are used as a contact region for connection to another wire.