Folded 6T SRAM Cell Layout for Square Aspect Ratio
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced SRAM devices face inefficiencies due to skewed aspect ratios and high bitline capacitance, leading to area inefficiencies and increased RC delays, which are exacerbated by the use of lower-level metals and unidirectional poly layers.
Innovation Solution
Implementing dual pairs of bitlines with alternating via connections and applying column select logic to access different wordlines, reducing bitline capacitance and improving aspect ratios, while also restructuring the underlying poly layer to create a more square bit cell layout with dual vertical wordlines and bitlines, thereby reducing RC delays and metal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If unidirectional poly layers are used in advanced SRAM devices, then manufacturing capability is improved, but the aspect ratio becomes skewed (taller and narrower)
Solution Approach 1:
The patent introduces multiple metal layers (M0, M1, M2) stacked vertically to route bitlines and wordlines in different spatial dimensions. This allows the SRAM cell to maintain a more square footprint by utilizing the third dimension (vertical stacking) for signal routing, thereby resolving the skewed aspect ratio issue while preserving manufacturing compatibility with unidirectional poly processes
2Loss of time
If metal resistance is reduced by using lower level metals, then RC delays decrease, but manufacturing precision becomes more difficult
Solution Approach 1:
The patent employs a composite multi-layer metal structure where different metal layers (M0, M1, M2) with different electrical and fabrication characteristics are stacked and interconnected. This composite approach allows optimization of RC delays by utilizing lower-level metals for critical paths while maintaining manufacturing precision through the use of upper-level metals that are easier to fabricate with standard processes
3Productivity
If bitline capacitance is reduced, then performance and power consumption improve, but area increases due to flying bitline scheme requirements
Solution Approach 1:
The patent utilizes vertical stacking of metal layers to create three-dimensional bitline routing paths. By routing bitlines across multiple stacked layers rather than extending them horizontally in a single plane, the effective bitline length is reduced, thereby decreasing capacitance and improving performance without requiring additional lateral area or flying bitline structures
Data Source
AI summary
A layout for a 6T SRAM cell is disclosed. The cell layout takes a conventional 6T SRAM cell layout and restructures the layout into a more square cell layout with a single p-channel and a single n-channel across the width of the cell. Restructuring the cell layout reduces the height of wordlines and allows dual wordlines to be placed in the cell to reduce wordline resistance in the cell. Dual pairs of bitlines may also be placed in separate metal layers in the cell layout to reduce bitline resistance.