Folded Series Switch Layout With Shared Source/Drain Regions
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Solution Overview
Problem
Previous chip layout approaches result in large parasitic resistances between transistors due to inefficient metal routing, which reduces performance as process nodes continue to scale down, necessitating an area-efficient layout technique that reduces routing resistance.
Innovation Solution
The implementation of source/drain sharing between transistors, where transistors share at least one source/drain, to reduce parasitic resistances by eliminating or minimizing the need for metal routing between them, using layout techniques that optimize gate and active region configurations to enhance area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional metal routing is used to interconnect transistors, then transistor interconnection is achieved, but parasitic resistance increases and area efficiency decreases
Solution Approach 1:
The patent merges the source/drain regions of multiple transistors into a shared structure. Specifically, a first source/drain region is shared between a first transistor and a second transistor, while a second source/drain region is shared between the second transistor and a third transistor. This merging eliminates the need for metal routing between these transistors, directly reducing parasitic resistance and improving performance.
2Ease of operation
If traditional metal routing is used to interconnect transistors, then transistor interconnection is achieved, but area utilization decreases and routing complexity increases
Solution Approach 1:
The patent merges the source/drain regions of multiple transistors into a shared structure. Specifically, a first source/drain region is shared between a first transistor and a second transistor, while a second source/drain region is shared between the second transistor and a third transistor. This merging eliminates the need for metal routing between these transistors, directly reducing parasitic resistance and improving performance.
Data Source
AI summary
A chip includes a first active region, first gates extending over the first active region in a first direction, wherein the first gates correspond to a first transistor, and second gates extending over the first active region in the first direction, wherein the second gates correspond to a second transistor.