Folded Thyristor RAM Cell Design for High Density
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Solution Overview
Problem
Current thyristor random access memory (TRAM) devices require significant surface area and inefficient manufacturing processes, limiting memory density and reliability.
Innovation Solution
A compact memory cell design featuring a folded semiconductor structure with p-n junctions and top-surface electrical contact points, allowing for reliable conductor wiring and efficient use of space, formed using silicon-on-insulator (SOI) or shallow trench isolation (STI) techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional TRAM device configuration is used, then memory storage function is achieved, but surface area consumption is high
Solution Approach 1:
The patent transforms the conventional planar memory cell layout into a three-dimensional folded structure. The folded conduction path configuration allows current to flow through a longer path within a smaller footprint area, effectively utilizing vertical space and reducing the horizontal surface area required for each memory cell, thereby increasing memory density.
Solution Approach 2:
The patent implements a folded conduction path that is essentially a nested configuration where the current path is folded back on itself multiple times within the same planar footprint. This nesting of the conduction path allows multiple segments of the current path to occupy overlapping or adjacent spatial regions, maximizing the use of available space and reducing the overall device area.
2Productivity
If conventional manufacturing methods are used, then device fabrication is achieved, but manufacturing efficiency and reliability are limited
Solution Approach 1:
The patent combines multiple manufacturing functions into integrated process steps. The folded structure is formed using standard semiconductor fabrication techniques where diffusion regions, isolation structures, and contact regions are created in an integrated manner rather than as separate sequential steps, thereby improving manufacturing efficiency and reducing process complexity.
Solution Approach 2:
The patent utilizes standard semiconductor doping parameters and fabrication conditions to create the folded structure. By employing conventional doping concentrations, thermal processing temperatures, and lithographic parameters, the design achieves its compact form factor without requiring exotic or complex manufacturing parameters, thus maintaining ease of manufacture while improving efficiency.
3Manufacturing precision
If deep trench ion implants are used, then doping is achieved, but manufacturing complexity and reliability are reduced
Solution Approach 1:
The patent extracts or eliminates the need for deep trench ion implantation by using alternative doping approaches. The folded conduction path is formed through diffusion-based methods or shallower implantation techniques that achieve the required doping profiles without the complexity and reliability issues associated with deep trench ion implants, thereby simplifying the manufacturing process while maintaining precision.
Data Source
AI summary
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device.