Folded Trench Gate Layout for Lower Channel Resistance
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Solution Overview
Problem
Existing trench transistors face challenges in reducing the high channel body resistance, particularly in low voltage applications, which affects their efficiency and energy consumption.
Innovation Solution
The design incorporates a nonlinear gate-oxide-semiconductor boundary, increasing the channel width by altering the gate shape to a piecewise linear or periodic rectangular form, while maintaining the same die-size, thereby enhancing the length of the conductive channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel body region is scaled down to reduce resistance, then the transistor resistance decreases, but the channel body region becomes too small to effectively control the drift region
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional folded gate structure. The gate is folded back on itself multiple times within the trench, creating a serpentine path that increases the gate-oxide-semiconductor boundary length without increasing the planar footprint. This dimensional transformation allows the channel body region to maintain adequate size while providing extended control over the drift region through the folded configuration.
Solution Approach 2:
The folded gate structure nests multiple gate segments within the same trench volume. Each fold creates additional gate-oxide-semiconductor boundaries that are nested within the three-dimensional space of the trench, effectively multiplying the control interface without requiring additional lateral or vertical space that would reduce the channel body dimensions.
2Length of moving object
If the gate shape is altered to increase channel width, then the conductive channel length increases, but the gate structure becomes more complex
Solution Approach 1:
The gate structure is segmented into multiple folded sections, each contributing to the overall gate-oxide-semiconductor boundary length. The gate is divided into discrete segments that are folded back sequentially, with each segment providing additional control boundary while maintaining a modular fabrication approach that manages complexity through repetition of standardized segments.
Solution Approach 2:
The gate structure employs curved or angled folds rather than sharp corners, creating a serpentine pattern that smoothly increases the boundary length. The curved geometry of the folded gate segments provides extended channel width while maintaining manufacturability through continuous deposition processes that can accommodate curved patterns.
Data Source
Figure 1~2
Figure 3~4A
Figure 4B~5
AI summary
A trench transistor with nonlinear gate-oxide-semiconductor boundary layout, and method of manufacture. The trench transistor comprises a gate region, an oxide region adjacent to the gate region, and a semiconductor region adjacent to the oxide region. The semiconductor region comprises a channel region along a gate-oxide-semiconductor boundary. The channel region configured to conduct current along the gate-oxide-semiconductor boundary when the transistor is turned on. The gate-oxide-semiconductor boundary has a nonlinear shape.