Unified Folding ADC Architecture Without a Coarse Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional folding ADCs require a large number of comparators, especially as resolution increases, leading to increased power consumption, die area, and calibration difficulties due to the need for separate coarse and fine channels.
Innovation Solution
A unified architecture for folding ADCs that eliminates the coarse channel by embedding comparators at the outputs of cascaded folding amplifier stages, using a single set of cascaded folding stages and distributed fine comparators, and incorporating recursive error correction for improved alignment and calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional folding ADC architecture with separate coarse and fine channels is used, then conversion functionality is achieved, but the number of comparators increases leading to larger die area and higher power consumption
Solution Approach 1:
The patent merges the separate coarse and fine conversion channels into a unified architecture where a single set of cascaded folding amplifier stages serves both functions. The folding amplifier stages perform both coarse folding and fine resolution comparison in an integrated manner, eliminating the need for duplicate comparator circuits in separate channels.
Solution Approach 2:
The unified architecture makes the folding amplifier stages multi-functional, serving both as coarse conversion elements and fine resolution comparators. The same hardware infrastructure performs multiple functions that previously required separate dedicated circuits, reducing overall component count.
2Measurement precision
If conventional folding ADC architecture with separate coarse and fine channels is used, then conversion functionality is achieved, but power consumption increases due to large number of comparators
Solution Approach 1:
The patent merges the separate coarse and fine conversion channels into a unified architecture where a single set of cascaded folding amplifier stages serves both functions. The folding amplifier stages perform both coarse folding and fine resolution comparison in an integrated manner, eliminating the need for duplicate comparator circuits in separate channels.
Solution Approach 2:
The unified architecture makes the folding amplifier stages multi-functional, serving both as coarse conversion elements and fine resolution comparators. The same hardware infrastructure performs multiple functions that previously required separate dedicated circuits, reducing overall component count.
3Measurement precision
If conventional folding ADC architecture with separate coarse and fine channels is used, then conversion functionality is achieved, but calibration becomes more difficult due to alignment requirements between channels
Solution Approach 1:
The patent merges the separate coarse and fine conversion channels into a unified architecture where a single set of cascaded folding amplifier stages serves both functions. The folding amplifier stages perform both coarse folding and fine resolution comparison in an integrated manner, eliminating the need for duplicate comparator circuits in separate channels.
Solution Approach 2:
The patent extracts and eliminates the problematic separate coarse channel infrastructure, retaining only the unified folding amplifier stages that inherently provide both coarse and fine conversion capabilities without requiring separate channel alignment and calibration.
Data Source
AI summary
A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array (1-N) of cascaded folding amplifier stages, a distributed array of fine comparators, and an encoder. Each folding amplifier stage includes folding amplifiers that are configured to receive inputs from a prior stage, and also generate output signals for the next stage. The folding amplifiers output signals for a given stage are evaluated by a corresponding comparator stage, which may include multiple comparators, and also optionally coupled to an interpolator. The outputs of the comparators from all stages are collectively evaluated by the encoder, which generates the output of the folding ADC. Unlike conventional folding ADCs that require fine and coarse channels, the presently described folding ADC provides conversion without the need for a coarse channel. The encoder can also be arranged to facilitate recursive error correction.


