Folding ADC Architecture for Full-Range Accurate Quantization
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Solution Overview
Problem
Current algorithmic A/D converters are limited by analog errors that reduce the effective input voltage range that can be accurately quantized to digital values, leading to saturation issues and reduced accuracy.
Innovation Solution
The proposed A/D converter employs a folding stage to initially fold the input voltage into sub-ranges, followed by algorithmic conversion stages that adjust the residue voltage using cyclic voltage offsets, allowing for accurate quantization across the full input range without saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital calibration is performed to correct analog errors in algorithmic A/D converters, then measurement precision is improved, but the effective input voltage range is reduced due to saturation
Solution Approach 1:
The input voltage range is divided into multiple sub-ranges, with each sub-range handled by a dedicated algorithmic A/D converter stage. The folding stage determines which sub-range the input voltage falls into, and only the relevant stage processes that specific range. This segmentation prevents saturation in individual stages while maintaining full-scale input range capability.
Solution Approach 2:
A folding stage is introduced as an intermediary component between the input and the algorithmic A/D converter stages. This folding stage includes folding comparators that determine the appropriate sub-range and generate control signals to select the correct reference voltage subset, enabling the system to handle full-scale inputs without saturating individual conversion stages.
2Device complexity
If algorithmic A/D converter architecture is used to reduce hardware requirements, then device complexity is reduced, but analog errors (zero-order and first-order errors) increase
Solution Approach 1:
The conversion process is segmented into multiple stages, each handling a specific sub-range with dedicated reference voltages. This allows each stage to operate within optimized parameters, reducing the impact of analog errors while maintaining the algorithmic architecture's hardware efficiency.
Solution Approach 2:
The system dynamically changes parameters (reference voltage selection) based on the input sub-range determined by the folding stage. By selecting appropriate reference voltages for each sub-range, the system optimizes conversion accuracy for different input levels while maintaining the efficient algorithmic architecture.
Data Source
AI summary
An A/D converter including a folding stage and a plurality of conversion stages is described. The folding stage determines a sub-range in which an input analog voltage falls and adjusts the input analog voltage by a folding voltage offset corresponding to the determined sub-ranges to produce a residue voltage. Each following converter stage determines a voltage range in which the residue voltage falls. The converter stage multiplies the residue voltage by a factor of N to produce an intermediate voltage. The conversion stage selects a cyclic voltage offset corresponding to the sub-ranges in which the residue voltage falls and adjusts the intermediate voltage by the cyclic voltage offset to produce a new residue voltage.