Folding ADC Encoder Using Mid-Fold Comparison for Offset Tolerance
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Solution Overview
Problem
Existing folding analog to digital converters (ADCs) suffer from errors in the coarse converter that lead to significant deviations in the final encoded signal due to offset issues, as they typically specify sections based on local maxima/minima, which can be incorrect.
Innovation Solution
A folding ADC design with a coarse voltage comparison point set in the middle of a fold, utilizing a coarse ADC comparator, a folder, an up encoder, and a fold information generator with logical combiners to determine the correct fold for an analog voltage, allowing for cyclical outputs and reduced comparator count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a folding ADC is used to reduce comparator count and area, then device complexity and area are reduced, but measurement precision deteriorates due to errors in the coarse converter creating large errors in the final encoded signal
Solution Approach 1:
The patent introduces an intermediary encoding scheme that processes the outputs of both coarse and fine ADCs before combining them. The encoder uses intermediate variables and logical operations to determine the final digital output, acting as a mediator that corrects errors from the coarse converter and prevents them from propagating to the final result.
Solution Approach 2:
The patent implements feedback mechanisms where the encoder continuously monitors the outputs of coarse and fine ADCs and adjusts the final encoding based on detected errors. The encoder uses feedback from the comparison results to correct offset errors and ensure accurate final digital representation despite imperfections in the folding architecture.
2Ease of operation
If coarse ADC specifies sections based on local maxima/minima, then the folding operation can be performed, but reliability deteriorates because offset errors can specify wrong sections leading to great deviations in final code
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing encoding tables that map coarse and fine ADC outputs to correct final codes. These pre-computed lookup tables account for potential offset errors and section boundary issues, allowing the system to reliably determine correct sections without being vulnerable to offset variations during operation.
Solution Approach 2:
The patent changes the parameter of voltage comparison points from being fixed at local maxima/minima to being dynamically adjusted based on offset compensation. The system modifies the effective comparison thresholds to account for detected offsets, ensuring that section specification remains reliable even when component variations cause shifts in voltage levels.
3Measurement precision
If precise comparator transitions are used to maintain accuracy, then measurement precision is maintained, but device complexity increases due to stricter manufacturing requirements and additional calibration circuitry
Solution Approach 1:
The patent employs a software-based encoding solution that replaces the need for expensive, high-precision hardware comparators. By using logical operations and lookup tables in the encoding stage, the system achieves high measurement precision with standard, lower-cost comparators, effectively trading hardware complexity for computational logic.
Solution Approach 2:
The patent substitutes the mechanical approach of using ultra-precise analog comparators with a digital logic-based encoding system. Instead of relying on precise analog voltage comparisons throughout the system, the invention uses digital logical operations to determine the final code, replacing the need for mechanically precise component transitions with robust digital logic that is tolerant of analog imperfections.
Data Source
AI summary
An apparatus comprises: a coarse voltage level comparator that generates a coarse voltage level comparison; a folder, a fine analog to digital (ADC) comparator coupled to an output of the folder, wherein an output of the fine ADC is cyclical; an up encoder coupled to an output of the fine ADC encoder, the up encoder configured to output a first value if the cyclical output of the fine ADC is in a defined downward transition; and a fold information generator coupled to an output of the up encoder, wherein the fold information generator is configured to generate a determination as to in which fold an analog voltage occurs.