Folding Column Adder CIM Circuit for Accurate Edge AI Compute
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Solution Overview
Problem
Conventional computation-in-memory processes using analog signals result in inaccurate neural network computations, and there is a need for more efficient processing of machine learning model data, particularly in edge devices with power and packaging constraints.
Innovation Solution
A circuit and method for in-memory computation using digital signals, incorporating memory cells configured to store neural network weights, addition circuits, and an accumulator to perform accurate computations, with a folding architecture allowing bit-size configurability and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional CIM processes use analog signals for computation, then computation can be performed in memory, but the computation results are inaccurate
Solution Approach 1:
The patent changes the fundamental parameter of signal representation from analog to digital domain. Memory cells store weights as digital values (e.g., 2's complement binary numbers) rather than analog conductance levels, and all computations are performed using digital logic circuits (adders, multiplexers) that operate on digital signals, thereby eliminating analog precision issues while maintaining in-memory computation capability
Solution Approach 2:
The patent replaces the analog physical mechanism (conductance-based multiplication) with digital logical operations. Instead of relying on analog signal properties for computation, the system uses digital logic gates and arithmetic circuits to perform computations on digitally stored weight values, substituting a more precise digital mechanism for the imprecise analog mechanism
2Productivity
If dedicated hardware accelerators are used for machine learning processing, then processing capacity is enhanced, but space and power consumption increase
Solution Approach 1:
The patent merges the memory storage function with the computation function into a single integrated structure. Memory cells that normally only store data are used to hold weight values, while dedicated adder circuits perform computations directly on these stored values, eliminating the need for separate processing units and reducing overall system power consumption while maintaining high processing capacity
Solution Approach 2:
The memory structure serves multiple functions: it stores weight values for neural network computations, performs arithmetic operations through integrated adder circuits, and can be reconfigured for different computational tasks. This multi-functionality reduces the need for dedicated accelerator hardware, thereby reducing power consumption while maintaining productivity
3Adaptability or versatility
If data is moved across common data busses for processing, then data can be shared between components, but power usage increases and latency is introduced
Solution Approach 1:
The patent segments the computation process into column-wise operations, where each column has dedicated adder circuits that process data locally. This segmentation allows parallel processing of multiple data elements simultaneously, reducing the time required for data sharing and computation while maintaining the ability to share results across the system
4Productivity
If more processing capabilities are added to edge devices, then machine learning tasks can be performed locally, but packaging constraints are exceeded
Solution Approach 1:
The patent combines memory storage and computation functions into a single integrated structure, eliminating the need for separate processing units. This merging reduces the overall device footprint while maintaining local processing capability, as the same memory cells that store data also enable computations through integrated adder circuits
Solution Approach 2:
The memory structure serves multiple functions including data storage, weight storage, and computation execution. This multi-functionality allows edge devices to perform machine learning tasks locally without requiring additional dedicated processing hardware, thereby reducing packaging constraints while maintaining productivity
Data Source
AI summary
Certain aspects provide an apparatus for performing machine learning tasks, and in particular, to computation-in-memory architectures. One aspect provides a circuit for in-memory computation. The circuit generally includes: a plurality of memory cells on each of multiple columns of a memory, the plurality of memory cells being configured to store multiple bits representing weights of a neural network, wherein the plurality of memory cells on each of the multiple columns are on different word-lines of the memory; multiple addition circuits, each coupled to a respective one of the multiple columns; a first adder circuit coupled to outputs of at least two of the multiple addition circuits; and an accumulator coupled to an output of the first adder circuit.