Fo-WLCSP Polymer Layer Interconnects for Reduced Bump Pitch
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Solution Overview
Problem
Conventional fan-out wafer level chip scale packages (Fo-WLCSP) are limited by the height of the encapsulant, which restricts bump arrangement options, bump size, and input/output (I/O) count, making it difficult to achieve smaller footprint and higher density semiconductor devices.
Innovation Solution
The method involves forming semiconductor devices with conductive layers and vias separated by polymer layers, eliminating the need for encapsulant around the semiconductor die, thereby reducing bump pitch and size, and increasing I/O count and arrangement options.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encapsulant is used around semiconductor die, then structural support and environmental isolation are provided, but package height increases and bump arrangement options are restricted
Solution Approach 1:
The patent removes the encapsulant from the package structure and replaces it with polymer layers that perform the same protective functions. This extraction of the encapsulant eliminates the height restriction while maintaining environmental isolation through the polymer encapsulation layers formed over the interconnect structure.
Solution Approach 2:
The patent changes the material parameter from traditional encapsulant to polymer layers, which have different physical properties including lower height profile. This parameter change allows the package to achieve the same protective function with reduced height, enabling finer bump pitch and higher I/O counts.
2Adaptability or versatility
If encapsulant height is increased to accommodate bumps, then bump size and arrangement are constrained, but I/O count is limited
Solution Approach 1:
By removing the encapsulant constraint, the patent enables bump arrangements that would otherwise be impossible. The polymer layer replacement allows bumps to be positioned closer together with greater flexibility in arrangement patterns, directly increasing the number of I/O connections achievable on the package.
3Area of stationary object
If conventional encapsulant structure is used, then package footprint is larger, but smaller footprint devices cannot be achieved
Solution Approach 1:
The removal of the encapsulant and replacement with polymer layers enables reduced bump pitch that would be constrained by encapsulant height. This extraction allows the package footprint to be minimized while maintaining manufacturing precision for finer pitch dimensions.
Data Source
AI summary
A Fo-WLCSP has a first polymer layer formed around a semiconductor die. First conductive vias are formed through the first polymer layer around a perimeter of the semiconductor die. A first interconnect structure is formed over a first surface of the first polymer layer and electrically connected to the first conductive vias. The first interconnect structure has a second polymer layer and a plurality of second vias formed through the second polymer layer. A second interconnect structure is formed over a second surface of the first polymer layer and electrically connected to the first conductive vias. The second interconnect structure has a third polymer layer and a plurality of third vias formed through the third polymer layer. A semiconductor package can be mounted to the WLCSP in a PoP arrangement. The semiconductor package is electrically connected to the WLCSP through the first interconnect structure or second interconnect structure.