Fo-WLCSP Interconnect Adhesion via Insulating Layer Openings
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Solution Overview
Problem
The adhesion between the first passivation layer and encapsulant in fan-out wafer level chip scale packages (Fo-WLCSPs) is weak, leading to potential device failure during reliability tests or in the field.
Innovation Solution
Forming openings through an insulating layer over the encapsulant to enhance the adhesion of the interconnect structure, which involves depositing an encapsulant, removing a portion of the insulating layer to expose contact pads, and forming conductive layers and redistribution layers directly on the encapsulant for improved anchoring of bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a first passivation layer is formed over the encapsulant in a conventional Fo-WLCSP, then the encapsulant is protected, but the adhesion between the passivation layer and encapsulant is weak leading to potential device failure
Solution Approach 1:
The patent applies preliminary action by forming openings through the insulating layer before depositing the passivation layer. This pre-prepared surface structure with exposed encapsulant areas allows the passivation layer to form stronger mechanical interlocks and chemical bonds, preventing adhesion failures during subsequent reliability testing or field operation.
Solution Approach 2:
The patent implements local quality by creating a non-uniform surface structure with alternating regions of insulating layer and exposed encapsulant. This localized variation in surface properties enables different adhesion mechanisms in different areas, with the exposed encapsulant regions providing enhanced anchoring points that strengthen overall adhesion without compromising the protective function across the entire surface.
2Reliability
If openings are formed through the insulating layer to expose contact pads, then adhesion is enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the insulating layer into regions that are removed (forming openings) and regions that are retained. This segmented approach creates discrete exposure zones that simplify the subsequent passivation layer deposition process, as the patterned surface provides natural alignment features and reduces the need for complex masking operations compared to fully removing or uniformly treating the entire insulating layer.
Data Source
AI summary
A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.