Multi-Chip Packaging Layout for FOPLP Displacement Control
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Solution Overview
Problem
Fan-out panel level packaging (FOPLP) processes face challenges with chip displacement, leading to yield loss, especially in multi-chip or advanced 2.5D/3D heterogeneous integration designs, where large displacements result in scrapped products.
Innovation Solution
Incorporating spacing elements and alignment marks in the packaging process to control chip displacement, with a ratio of distance to width between elements ranging from 1 to 1.3, allowing for improved alignment and reduced displacement during bonding and molding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip displacement is not controlled during molding, then manufacturing process is simple, but packaging yield decreases due to scrapped products
Solution Approach 1:
Alignment marks are formed on the substrate before chip mounting and molding processes. These pre-formed marks enable precise measurement and compensation of chip displacement during subsequent manufacturing steps, allowing yield improvement without fundamentally changing the molding process itself
Solution Approach 2:
Alignment marks serve as an intermediary reference system between the substrate and chips. By providing visible markers that can be detected and used for measurement, they mediate the displacement control function without requiring direct modification of the chips or substrate structure
2Measurement precision
If substrate engraving is used for alignment marks, then alignment precision improves, but manufacturing cost increases
Solution Approach 1:
The alignment marks are formed using a inexpensive photoresist layer that can be easily deposited and removed, replacing the need for costly substrate engraving. The photoresist marks serve their alignment purpose effectively without requiring permanent modification of the substrate
Solution Approach 2:
The mechanical substrate engraving process is replaced with a chemical/photochemical process using photoresist material deposition and patterning. This substitution uses material deposition rather than mechanical removal, significantly reducing manufacturing complexity and cost
Data Source
AI summary
An electronic device is provided. The electronic device includes a plurality of spacing elements, a first electronic unit and a second electronic unit, a protective layer and a connecting member. The first electronic unit and the second electronic unit are individually disposed between two adjacent spacing elements. The protective layer surrounds the spacing elements, the first electronic unit and the second electronic unit. The first electronic unit is electrically connected to the second electronic unit via the connecting member. In a direction that is perpendicular to a normal direction of the electronic device, the first electronic unit has a first width, and a first distance is between the two adjacent spacing elements. A ratio of the first distance to the first width is greater than or equal to 1 and less than or equal to 1.3. A method of manufacturing an electronic device is also provided.


