FOPLP Pad Structure With Sidewall Sealing for Alignment Stability

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Solution Overview

Problem

The alignment of internal and external pads in fan-out plate level package (FOPLP) technology is prone to errors due to plate expansion and retraction during processing, leading to poor pattern alignment accuracy and increased risk of pad offset, which affects product yield.

Innovation Solution

A packaging method involving the formation of first and second pads with controlled orthographic projections, followed by sealing with materials to fix their spacing and prevent offset, and subsequent sealing of chips to enhance reliability and accommodate larger chip sizes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If traditional FOPLP processing is used, then chip miniaturization is achieved, but alignment accuracy deteriorates due to plate expansion and retraction

Engineering Contradiction:
Improvechip sizeVSAvoidalignment accuracy
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The pad structure is segmented into multiple levels: internal pad, first pad, and second pad. The internal pad remains fixed on the carrier while the first and second pads are formed on its side surface, creating a hierarchical structure that separates the mounting function from the external connection function, thereby eliminating alignment errors caused by plate deformation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The pad structure transitions from a traditional two-dimensional planar arrangement to a three-dimensional vertical arrangement. Pads are formed on the side surface of the internal pad at different heights, utilizing the vertical dimension to establish precise spatial relationships that are immune to horizontal plate expansion and retraction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If plate expansion and retraction occur during processing, then manufacturing flexibility is maintained, but pad alignment deteriorates

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidpad alignment
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The internal pad is formed and fixed on the carrier before the chip mounting process. The first and second pads are subsequently formed on the side surface of the internal pad at predetermined positions. This preliminary establishment of the internal pad structure provides a stable reference that is not affected by subsequent plate expansion or retraction during processing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The internal pad serves as an intermediary structure between the carrier and the external pads. It is fixed to the carrier and provides a stable platform for forming the first and second pads on its side surface, isolating the external pad positions from the effects of carrier expansion and retraction.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If grinding is performed to expose the internal pad surface, then external pad alignment is enabled, but alignment error increases

Engineering Contradiction:
Improveexternal pad accessibilityVSAvoidpattern alignment accuracy
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

Instead of grinding the carrier to expose the internal pad surface for alignment (traditional approach), the invention inverts the approach by forming the external pads on the side surface of the internal pad. This eliminates the need for grinding and the associated alignment errors, as the external pads are directly formed at their final positions.

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS12610847B2Packaging method and package member
Publication Date: 2026.04.21 SKY CHIP INTERCONNECTION TECH CO LTD
  • US12610847B2 patent drawing
  • US12610847B2 patent drawing
  • US12610847B2 patent drawing

AI summary

A packaging method includes: obtaining a carrier and processing a first pad on a side surface of the carrier; processing a second pad on a side surface of the first pad away from the carrier; obtaining a first sealing material, pressing the first sealing material with the second pad, the first pad, and a side surface of the carrier on which the first pad is arranged to form a first sealing member; processing a chip pad on a side surface of each first pad away from the second pad; mounting a chip on at least one chip pad; obtaining a second sealing material, pressing the second sealing material with the chip, a side surface of the chip pad away from the second pad, and a side surface of the first sealing member near the first pad, to form a second sealing member.