Forced C-State Entry for Deep Standby Power Validation

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Solution Overview

Problem

Computing systems face inefficiencies in entering low power states due to latency tolerance issues, where some devices fail to properly sequence down to off states, potentially blocking the system's entry into deep low power states, and existing methods require hardware, driver, and BIOS support for every device, which is not always available.

Innovation Solution

The implementation of a Forced Cx state mechanism that allows the system to ignore latency tolerance information and enter a low power state, such as Forced C10, by communicating directly between the SoC North and South power controllers, enabling the system to transition to a low power state without honoring latency tolerance requests, thereby facilitating testing and validation of low power states without full hardware support.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the system enters deep low power states (e.g., C10) by ignoring latency tolerance information, then power efficiency is improved, but system reliability may deteriorate due to potential blocking by devices that fail to sequence down properly

Engineering Contradiction:
Improvepower efficiencyVSAvoidsystem reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The Forced Cx state mechanism applies partial action by selectively ignoring latency tolerance information only for the specific purpose of entering deep low power states, while maintaining normal latency tolerance handling for other system operations. This allows the system to achieve deep power states without completely disabling reliability checks in all contexts.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The Forced Cx state acts as an intermediary mechanism between the power management controllers (North and South) that enables direct communication and coordination for entering low power states without being blocked by devices that fail to properly sequence down. This intermediary state allows the system to bypass problematic latency tolerance checks while maintaining overall system control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the system requires full hardware, driver, and BIOS support for every device to enter low power states, then system stability is improved, but device complexity and ease of implementation worsen

Engineering Contradiction:
Improvesystem stabilityVSAvoidhardware support requirements
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The Forced Cx state mechanism extracts the requirement for full hardware, driver, and BIOS support from the low power state entry process. By creating a forced entry mechanism that operates independently of these support requirements, the system can enter deep low power states even when some devices lack proper support, thereby reducing the complexity burden on individual components.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The Forced Cx state mechanism provides universal functionality by enabling low power state entry across different device configurations and support levels. Instead of requiring each device to have specific hardware, driver, and BIOS support, the forced mechanism works universally across the system, allowing any device to coexist in the low power state entry process without preventing others from entering low power states.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If the system honors latency tolerance information from all devices, then wake-up reliability is improved, but wake-up time increases due to sequencing delays

Engineering Contradiction:
Improvewake-up reliabilityVSAvoidwake-up time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The Forced Cx state mechanism performs preliminary action by pre-coordinating the low power state entry between North and South power controllers before latency tolerance issues can block the process. This preliminary coordination allows the system to establish a synchronized entry point that reduces wake-up time while maintaining reliability through pre-planned wake-up sequencing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3475783B1Systems, methods and devices for standby power entry without latency tolerance information
Publication Date: 2022.10.26 INTEL CORP
  • EP3475783B1 patent drawingFigure 1
  • EP3475783B1 patent drawingFigure 2
  • EP3475783B1 patent drawingFigure 3

AI summary

Standby power entry can be performed without latency tolerance information. The embodiments disclosed herein enable a power delivery system of a computing system to enter the requested low power state while ignoring any latency tolerance information throughout the platform. For example, an operating system (OS) can request a Forced Cx state (also known as a Forced C state), such as a Forced C10 state, allowing the system to ignore any latency tolerance information throughout the platform. This Forced Cx state can be used as a test mechanism to determine if a problematic device or integrated circuit is blocking entry into the low power state.