Fork-FET Dielectric Isolation Structure for Fin Cut Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing nanosheet semiconductor devices face challenges in fin cut lithography misalignment, leading to variations in effective gate width ratio and performance degradation due to parasitic source and drain leakage, particularly in aggressively scaled gate lengths.
Innovation Solution
Implementing bottom dielectric isolation (BDI) in Fork-FET devices to enhance electrical performance by isolating source and drain regions from the substrate, using a dielectric layer to stabilize the structure and mitigate misalignment issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fin cut lithography is used to define Fork-FET devices, then device patterning is achieved, but misalignment occurs leading to variations in effective gate width ratio
Solution Approach 1:
The patent performs preliminary actions by forming the bottom dielectric isolation layer and central vertical pillar before the fin cut lithography step. This preliminary structuring establishes reference features that guide subsequent alignment operations, ensuring that the fin cuts are made at precise locations relative to the device geometry, thereby preventing misalignment and variations in gate width ratio.
Solution Approach 2:
The patent replaces reliance on purely lithographic alignment (mechanical/optical system) with a self-aligned approach using deposited and etched dielectric structures. The bottom dielectric isolation and central pillar serve as physical references that define the fin cut locations through etch-stop mechanisms rather than relying solely on lithographic pattern alignment, thus eliminating misalignment issues.
2Productivity
If gate length is aggressively scaled to improve device density, then transistor size is reduced, but parasitic source and drain leakage increases causing performance degradation
Solution Approach 1:
The patent segments the channel region from the source and drain regions by introducing a bottom dielectric isolation layer at the substrate interface. This segmentation creates an insulating barrier that electrically isolates the channel, preventing parasitic leakage paths between source and drain that would otherwise occur due to aggressive scaling. The central vertical pillar further segments the device structure to enable independent control and isolation.
Solution Approach 2:
The bottom dielectric isolation layer acts as an intermediary element between the substrate and the channel region. This intermediate dielectric layer provides electrical isolation and prevents direct interaction between the substrate and the scaled channel, thereby blocking parasitic leakage paths while allowing the channel to maintain its scaled dimensions for high device density.
3Reliability
If bottom dielectric isolation is formed to isolate source and drain regions, then parasitic leakage is reduced, but additional process steps are required
Solution Approach 1:
The patent merges multiple functions into the bottom dielectric isolation layer formation process. The same dielectric deposition and etch processes that create the bottom isolation layer also form the central vertical pillar structure and define the fin cut regions. By combining these functions into a single integrated process sequence, the patent achieves improved electrical performance without proportionally increasing process complexity.
Solution Approach 2:
The bottom dielectric isolation layer serves multiple functions simultaneously: it provides electrical isolation to reduce parasitic leakage, serves as a reference structure for fin cut alignment, and acts as a mechanical support for the scaled channel. The central vertical pillar also serves multiple purposes including structural support, alignment reference, and potential gate control. This multi-functionality reduces the need for separate dedicated process steps.
Data Source
AI summary
A semiconductor apparatus includes a substrate; a central vertical pillar of dielectric material protruding upward from the substrate; a left plurality of semiconductor fins protruding horizontally from a left side of the central vertical pillar above the substrate; a right plurality of semiconductor fins protruding horizontally from a right side of the central vertical pillar opposite the left plurality of semiconductor fins; a gate stack surrounding the central vertical pillar and the left and right pluralities of semiconductor fins; and a bottom dielectric insulating layer protruding horizontally left and right of the central vertical pillar below the left and right pluralities of fins and adjacent to the substrate.