Fork-Nanosheet eFuse Cells With Dielectric Fins for Area Reduction
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Solution Overview
Problem
The challenge in integrating electronic fuses (efuses) into advanced integrated circuits is that their size reduction has not kept pace with the miniaturization of transistor features, leading to increased real estate requirements, making it difficult to accommodate them in evolving memory devices.
Innovation Solution
The efuse device incorporates a fork-nanosheet configuration where sub-transistors are connected in parallel, with a dielectric fin structure separating nanostructures, allowing for a significant reduction in area and enabling more efuse cells to be integrated within a given space, using a metal structure as the fuse resistor and sub-transistors formed over a semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional efuse structures are used, then the device can store data non-volatily, but the area occupied by efuse cells increases
Solution Approach 1:
The efuse device is divided into multiple sub-transistors (first sub-transistor and second sub-transistor) connected in parallel, each with its own channel structure. This segmentation allows the current path to be distributed across multiple smaller components rather than requiring a single large transistor, thereby reducing the overall area while maintaining the non-volatile data storage function through the fuse resistor.
Solution Approach 2:
The channel structures of the sub-transistors extend in a first lateral direction, while the gate structures wrap around them in a second lateral direction perpendicular to the first. This three-dimensional gating arrangement allows for more efficient space utilization, enabling the efuse cell to occupy less area compared to traditional planar transistor designs.
2Productivity
If efuse size is reduced to match transistor miniaturization, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The gate structures are configured to wrap around the channel structures, with the first gate structure surrounding the first channel structure and the second gate structure surrounding the second channel structure. This nested arrangement allows for compact integration of multiple functional elements within a small footprint, improving integration density while using standard fabrication processes for forming the nested structures.
Data Source
AI summary
A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.