Fork Sheet Transistor Layout Using a Backside Dielectric Pillar
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Solution Overview
Problem
Existing semiconductor devices fail to integrate and separate fork sheet transistors effectively, with existing semiconductor devices failing to integrate and separate fork sheet transistors effectively, with existing semiconductor devices failing to integrate and separate fork sheet transistors effectively, with existing semiconductor devices failing to integrate and separate fork sheet transistors efficiently.
Innovation Solution
A semiconductor device is provided with a backside dielectric pillar that extends from the backside of the device into the frontside, separating a pair of fork sheet transistors, and includes a backside BEOL structure electrically connected to the source/drain regions of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dielectric wall structure is introduced between PFET and NFET to achieve tri-gate forked structure, then tighter n-to-p spacing and higher performance are achieved, but device complexity increases due to the need for separate NFET and PFET devices
Solution Approach 1:
The device is segmented into frontside and backside components, with the dielectric wall extending from the backside to the frontside. This segmentation allows the dielectric structure to serve dual purposes: providing mechanical support from the backside and electrical isolation at the frontside, thereby reducing overall device complexity while maintaining tight spacing
Solution Approach 2:
The dielectric wall structure is extended into the vertical dimension by having it originate from the backside substrate and penetrate through to the frontside. This three-dimensional configuration allows the same structure to provide both mechanical anchoring and electrical isolation functions, reducing the need for separate components
2Productivity
If fork sheet transistors are integrated in the same structure, then integration efficiency is improved, but isolation between transistors becomes more difficult
Solution Approach 1:
The dielectric wall structure segments the shared substrate into distinct regions for NFET and PFET devices. By extending this dielectric barrier from the backside through to the frontside, reliable electrical isolation is achieved while both transistor types share the same integrated structure, maintaining high integration efficiency
Solution Approach 2:
The dielectric wall acts as an intermediary barrier between the NFET and PFET transistors. This intermediate structure provides the necessary electrical isolation while allowing both transistor types to be integrated in the same device, resolving the conflict between integration and isolation requirements
Data Source
AI summary
A semiconductor device is provided including a backside dielectric pillar that extends from the backside of the device into the frontside of the device where the backside dielectric pillar separates a pair of fork sheet transistors from each other.