Fork-Sheet Gate Isolation Layout for Precise Two-Stage Gate Cutting
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges in achieving precise control and alignment of isolation blocks for fork-sheet field effect transistors, leading to misalignment and over-etching issues, which affect the reliability and performance of transistors.
Innovation Solution
A two-staged gate cutting process using two different photomasks followed by etching steps is employed to form isolation blocks, allowing for precise control and better alignment, and reducing spacing requirements between adjacent nanostructures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-stage gate cutting process is used, then the fabrication process is simpler and faster, but misalignment and over-etching occur leading to poor manufacturing precision
Solution Approach 1:
The gate cutting process is divided into two distinct stages: first forming a preliminary gate structure with initial isolation blocks, then forming the final gate structure with precisely aligned isolation blocks. This segmentation allows each stage to be optimized independently, with the second stage focusing solely on achieving precise alignment without the constraints of the first stage.
Solution Approach 2:
The first stage performs preliminary gate formation and initial isolation block placement, creating a foundation structure. This preliminary action prepares the substrate and establishes reference features that guide the second stage, enabling the final precise alignment to be achieved more easily building upon the prepared structure.
2Area of moving object
If spacing between adjacent nanostructures is reduced to increase functional density, then chip area utilization improves, but alignment control becomes more difficult
Solution Approach 1:
By dividing the gate cutting into two stages with intermediate structure formation, the process can accommodate reduced spacing between nanostructures. The first stage establishes the minimum spacing requirements, while the second stage achieves precise alignment within that constrained space, enabling higher functional density without sacrificing alignment control.
3Reliability
If conventional gate cutting is used, then the process is simpler, but over-etching occurs affecting transistor reliability
Solution Approach 1:
The two-stage gate cutting process segments the etching operations, with the first stage performing preliminary etching to establish basic structures, and the second stage performing controlled etching for precise isolation block formation. This segmentation prevents over-etching by limiting each stage's etching depth and scope, ensuring transistor reliability while maintaining manageable process complexity through systematic division of operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces misalignment and over-etching, improving the reliability and performance of transistors by ensuring precise landing of isolation blocks on dielectric isolation walls.
Implementation Method 1
A two-staged gate cutting process using two different photomasks followed by etching steps is employed to form isolation blocks
Implementation Method 2
followed by etching steps is employed to form isolation blocks
Data Source
AI summary
A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure. The first isolation block has an extending depth smaller than an extending depth of the second isolation block.