Fork Stack Semiconductor Architecture for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional semiconductor devices face challenges with low current and low power performance due to limitations in electrical properties such as threshold voltage and parasitic capacitance, which hinder their effectiveness in high current and power trade-off applications.
Innovation Solution
A semiconductor architecture featuring a substrate with n-type and p-type transistors, each comprising multiple finger sub-devices with stacked semiconductors and a dielectric barrier extending down one side, which reduces parasitic capacitance and enhances resistance-capacitance trade-off, allowing for high current and power performance. The architecture includes gate dielectric and metal gate layers to connect the sub-devices, enabling both fork stack and gate-all-around device configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional semiconductor devices use standard transistor architectures (MOSFET, FinFET, GAAFET), then manufacturing and electrical conduction are achieved, but parasitic capacitance remains high and current-power performance is limited
Solution Approach 1:
The semiconductor device is divided into multiple finger sub-devices (e.g., first, second, third, fourth finger sub-devices) with stacked semiconductor structures. This segmentation reduces parasitic capacitance by distributing the electrical load across multiple smaller units while maintaining high current drive capability through parallel operation of the fingers.
Solution Approach 2:
The patent transitions from planar 2D transistor structures to 3D stacked semiconductor architectures. The stacked semiconductor layers (e.g., first, second, third stacked semiconductors) extend the channel into the vertical dimension, increasing the effective channel area and drive current without proportionally increasing parasitic capacitance, thus improving the current-power performance ratio.
2Ease of manufacture
If dielectric isolation is used in conventional FS devices with multiple stacks of nanosheets/nanowires, then manufacturing complexity is reduced, but electrical properties such as threshold voltage and power performance trade-off are compromised
Solution Approach 1:
Dielectric barriers are selectively positioned only between specific finger sub-devices (e.g., between first and second finger sub-devices, and between third and fourth finger sub-devices) rather than uniformly across all structures. This local application maintains manufacturing simplicity while preserving electrical performance in critical regions where threshold voltage control and power efficiency are most needed.
3Area of stationary object
If multiple stacks of nanosheets/nanowires are arranged in single finger form, then device area is reduced, but electrical current and power performance are limited
Solution Approach 1:
The device employs multiple finger sub-devices (at least four fingers) arranged in parallel, each containing stacked semiconductor structures. This segmentation allows the device to maintain a compact footprint while achieving high electrical current and power performance through the parallel combination of multiple active channels, effectively distributing the performance across spatially separated but electrically parallel structures.
Solution Approach 2:
The patent utilizes vertical stacking of semiconductor layers within each finger to increase the effective channel area without proportionally increasing the planar device footprint. This 3D stacking approach, combined with multiple parallel fingers, maximizes the current drive capability and power performance within a limited area by exploiting the vertical dimension for additional conduction paths.
Data Source
AI summary
A semiconductor architecture includes a substrate, an n-type transistor, and a p-type transistor, each formed on the substrate. Each of the n-type transistor and the p-type transistor of the semiconductor architecture includes a plurality of finger sub-devices, and each finger sub-device of the plurality of finger sub-devices includes a plurality of stacked semiconductors. One or more of the finger sub-devices of the plurality of finger sub-devices for each of the n-type transistor and the p-type transistor is formed as a fork stack device including a dielectric barrier that extends down only one side of the stacked semiconductors.