Forked CFET Structure for Lower Gate Capacitance and CPP Scaling
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Solution Overview
Problem
Current integrated circuit (IC) fabrication technologies face challenges in scaling standard cells due to high gate capacitance and complex routability issues with existing FET architectures, which affect transistor density and interconnect complexity.
Innovation Solution
The implementation of a complementary FET (CFET) architecture with a stack of two transistors, each having forked semiconductor structures misaligned along the vertical or horizontal axis, allowing for reduced gate capacitance and enhanced contacted poly pitch (CPP) scaling, enabling easier backside power delivery and lower via resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional FET architectures are used, then transistor density can be maintained, but gate capacitance becomes high and routability becomes complex
Solution Approach 1:
The source and drain regions are segmented into multiple fingers (e.g., four fingers) that are distributed across the channel width. This segmentation reduces the gate capacitance by dividing the total gate-source and gate-drain overlap area into smaller segments, while also simplifying routability by providing multiple access points for interconnects.
Solution Approach 2:
The invention transitions from a planar FET layout to a three-dimensional stacked configuration where multiple FETs are vertically stacked. This dimensional change allows for increased transistor density without proportionally increasing the footprint area, while the forked finger configuration optimizes the spatial distribution of interconnect access points.
2Ease of manufacture
If conventional FET architectures are used, then manufacturing processes can be maintained, but gate capacitance increases affecting performance
Solution Approach 1:
The gate is segmented into multiple fingers that are separated by spacers. This segmentation reduces the total gate capacitance by minimizing the overlap area between the gate and source/drain regions, while the segmented structure can still be fabricated using standard CMOS processing techniques including spacer formation and selective etching.
Solution Approach 2:
The source and drain regions are configured with different local geometries - the source region has fingers extending in one direction while the drain region has fingers extending in the opposite direction. This local quality variation optimizes the electric field distribution and reduces parasitic capacitance while maintaining compatibility with conventional manufacturing processes.
3Area of stationary object
If standard cell scaling is attempted, then area reduction is achieved, but aspect ratio via resistance increases
Solution Approach 1:
By stacking multiple FETs vertically, the invention reduces the horizontal footprint area of the standard cell. The via structures are designed with optimized aspect ratios by utilizing the vertical stacking arrangement, allowing power and signal vias to access different levels of the stacked FETs without excessive length, thereby maintaining lower via resistance despite area scaling.
Solution Approach 2:
The forked finger configuration allows interconnect structures to be nested between the fingers, enabling efficient use of vertical space and reducing the need for long via paths. This nesting arrangement helps maintain via resistance at acceptable levels while achieving area reduction through compact stacking.
Data Source
AI summary
A CFET may include two or more transistors stacked over each other. A transistor may be a FET including a forked semiconductor structure. The source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. A branch may include a fin, nanoribbon, etc. The channel region may be between a branch of the source region and a branch of the drain region. The body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. The two bodies may be diagonally arranged with respect to the channel region. The body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.