Forked Lead Frame Layout for Low-Inductance Inverter Modules
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Solution Overview
Problem
Existing semiconductor module packages for driving inverters face challenges in minimizing inductance while maintaining high efficiency and stability under high voltage and current conditions, which affects their performance and size.
Innovation Solution
A semiconductor module package design that includes a specific arrangement of semiconductor chips and lead frames with fork-shaped leg portions and connections to minimize inductance without increasing package size, achieved through a series and parallel connection configuration of semiconductor chips and lead frames, allowing for efficient power distribution and reduced electrical flow length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If conventional semiconductor module package design is used, then package size can be maintained, but inductance cannot be minimized
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and connected through through-substrate conductors, utilizing the vertical dimension to reduce current path length and inductance without increasing the horizontal package footprint.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked vertically within the same horizontal footprint. The chips are nested in layers, with lower chips supporting upper chips, and electrical connections passing through intermediate layers, effectively nesting functional elements within a compact volume.
2Force
If series connection of semiconductor chips is used, then inductance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor functionality into multiple discrete chips, each performing a specific switching function. These segmented chips are connected in series through vertical stacking, allowing independent optimization of each chip while achieving reduced overall inductance through the series configuration.
Solution Approach 2:
The patent pre-configures each semiconductor chip with its own contact pads and connection structures before stacking. The through-substrate conductors are prepared in advance within the substrate, enabling simplified assembly where chips are sequentially stacked and connected without complex real-time routing operations.
3Length of stationary object
If vertical stacking of chips is implemented, then electrical flow length is minimized, but heat dissipation becomes more challenging
Solution Approach 1:
The patent introduces thermal interface materials and heat dissipation structures as intermediaries between the stacked semiconductor chips and the external heat sink. These intermediary elements facilitate efficient heat transfer from the densely packed chips without interfering with the electrical connections or increasing the electrical flow path length.
Data Source
AI summary
Provided is a semiconductor device. A semiconductor device is implemented as a semiconductor module package for driving an inverter, the semiconductor device may include: a first upper metal layer in which a plurality of first semiconductor chips implementing a switching pattern of a low voltage phase are disposed along a first row in a first direction; a first connection connecting the plurality of first semiconductor chips in series and extending to a second upper metal layer; and a first lead frame providing power to the semiconductor device from an external source through the second upper metal layer, wherein, in the second upper metal layer, a first vertically extending leg portion and a second vertically extending leg portion of the first lead frame forming a fork shape are disposed, and the first connection is disposed between the first vertically extending leg portion and the second vertically extending leg portion.