Forksheet Antifuse OTP Memory for Compact Reliable Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current antifuse-type one-time programming (OTP) memory technologies face challenges in efficiently programming and maintaining data storage states due to limitations in transistor design, particularly with the integration of forksheet transistors, which affect the reliability and durability of memory cells.
Innovation Solution
The development of an antifuse-type OTP memory using forksheet transistors with specific gate and spacer structures, where the gate dielectric layer is ruptured under controlled voltage stress to switch between high and low resistance states, enabling reliable programming and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional transistors are used in OTP memory, then the memory can be programmed once, but the circuit area is large and integration efficiency is low
Solution Approach 1:
The patent merges the N-type and P-type transistors into a single integrated forksheet transistor structure where both transistor types share common components including the substrate, isolation walls, nanowires, and gate structures. This merging eliminates the need for separate transistor implementations, significantly reducing the circuit area while maintaining the one-time programming functionality through the antifuse mechanism.
Solution Approach 2:
The patent transitions from planar transistor architecture to a three-dimensional forksheet transistor structure with vertical stacking of components. The N-type and P-type transistors are positioned in different vertical layers sharing horizontal components, utilizing the third dimension (vertical depth) to reduce planar area while maintaining functional separation and integration efficiency.
2Adaptability or versatility
If advanced transistor structures like forksheet transistors are integrated, then the area is reduced and programming capabilities are enhanced, but the device complexity increases
Solution Approach 1:
The forksheet transistor structure serves multiple functions simultaneously: it implements both N-type and P-type transistor operations, provides antifuse one-time programming capability, enables compact integration, and supports advanced process technologies. The shared components (substrate, isolation walls, nanowires, gate structures) perform multiple roles across different transistor types, reducing overall device complexity despite the advanced structure.
3Ease of manufacture
If planar transistors are used, then the manufacturing process is simple, but the area consumption is high and integration is limited
Solution Approach 1:
The patent adopts a three-dimensional vertical stacking architecture where N-type and P-type transistors are positioned in different vertical layers rather than occupying separate planar areas. This dimensional transition allows both transistor types to share horizontal space and common components, dramatically reducing circuit area while the manufacturing process leverages existing advanced semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and durability of OTP memory cells by allowing precise control over resistance states, improving data storage and retrieval processes through the use of forksheet transistors with optimized gate dielectric layer structures.
Implementation Method 1
the gate dielectric layer is ruptured under controlled voltage stress to switch between high and low resistance states
Data Source
AI summary
An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.