Forksheet Transistor Backbone Layout for Dense 3D Gate Scaling
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors poses challenges in maintaining mobility improvement and short channel control, particularly as dimensions approach the 10 nanometer node, and there is a trade-off between feature size and spacing in lithographic processes.
Innovation Solution
The implementation of forksheet transistors with backside self-aligned backbones, which allows for increased density and improved interconnection architectures by stacking transistor strata and using a backside self-aligned metal gate cut process to form the forksheet structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate and nanowire transistors are scaled to smaller dimensions, then device density is improved, but short channel control and mobility improvement deteriorate
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional forksheet architectures with vertical channels extending through multiple semiconductor layers. This dimensional change enables higher device density while maintaining effective gate control through the multi-gate configuration that surrounds the vertical channels from multiple directions, addressing both density and short channel control requirements
2Quantity of substance
If multi-gate and nanowire transistors are scaled to smaller dimensions, then device density is improved, but mobility improvement deteriorates
Solution Approach 1:
The patent employs composite semiconductor structures consisting of alternating layers of different semiconductor materials (e.g., Si/SiGe) to form the vertical channels. This composite material approach enables selective etching to create suspended nanowire channels while maintaining crystal orientation for improved carrier mobility, thus achieving high density without sacrificing mobility performance
3Quantity of substance
If the number of transistors per region is increased, then capacity is improved, but lithographic process constraints worsen
Solution Approach 1:
The invention moves transistor fabrication from a two-dimensional lithographic plane to a three-dimensional structure where vertical channels extend through multiple layers. This allows transistor density to be increased primarily through vertical stacking rather than lateral packing, thereby reducing the stringency of lithographic spacing requirements while maintaining manufacturing precision
Solution Approach 2:
The patent segments the transistor structure into multiple discrete semiconductor layers stacked vertically, with each layer potentially containing channels. This segmentation allows independent processing and relaxation of lithographic constraints in the lateral direction, as the critical transistor formation occurs through vertical layering rather than dense lateral patterning
Data Source
AI summary
Embodiments disclosed herein include forksheet transistor transistors with backside self-aligned backbones. In an example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires, a gate dielectric around the stack of nanowires, a gate electrode around the gate dielectric, a cut through the sub-fin structure, through the stack of nanowires, through the gate dielectric and through the gate electrode, and a dielectric backbone in the cut, wherein the gate dielectric is discontinuous between vertically adjacent ones of the stack of nanowires.