Forksheet Cell Backside Contacts for Gate Resistance and Density
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Solution Overview
Problem
Conventional semiconductor devices face challenges in further scaling due to issues such as increased gate resistance, yield loss, and space constraints in forksheet architecture, particularly with dielectric walls causing obstacles for shared gates and diffusion contacts.
Innovation Solution
Implementing a forksheet cell architecture with a dielectric wall that splits shared gates and nanosheets, using backside gate strap contacts and direct backside power connections to address resistance and space issues, enabling efficient channel formation and power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric wall is used to split shared gates in forksheet architecture, then channel separation and device reliability are improved, but gate resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent introduces backside gate strap contacts that extend the gate electrical connection to the backside of the dielectric wall, transforming a 2D planar connection problem into a 3D solution. This allows the gate signal to bypass the obstructive dielectric wall by traveling through the vertical dimension and making contact with the gate from the opposite side, thereby reducing gate resistance while preserving the dielectric wall's channel separation function.
Solution Approach 2:
The backside gate strap contact acts as an intermediary element that mediates between the gate and the dielectric wall. Instead of allowing the dielectric wall to directly obstruct the gate connection, the patent introduces this intermediate conductive structure that bridges the gap, enabling electrical connection while maintaining the physical separation provided by the dielectric wall.
2Reliability
If dielectric walls are implemented to separate channels in forksheet devices, then channel isolation is improved, but space constraints and cell density are worsened
Solution Approach 1:
The patent utilizes the vertical dimension by placing gate strap contacts on the backside of the dielectric wall, allowing electrical connections to be made without requiring additional horizontal space. This 3D approach to connectivity enables the circuit to bypass the space-consuming dielectric wall structure, thereby improving cell density while maintaining channel isolation.
Solution Approach 2:
The patent merges the gate connection function with the backside of the dielectric wall structure. By integrating the gate strap contact into the backside surface of the same structure that provides channel isolation, the patent eliminates the need for separate isolation structures, thereby reducing overall cell area while maintaining both isolation and connectivity functions.
3Ease of manufacture
If conventional frontside gate contacts are used, then manufacturing is simpler, but parasitic capacitance and gate resistance increase
Solution Approach 1:
The patent inverts the conventional approach by moving the gate contact from the frontside to the backside of the dielectric wall structure. This inversion allows the gate signal to be applied from the opposite direction, bypassing the parasitic capacitance associated with frontside contacts and reducing gate resistance, while the manufacturing process remains compatible with standard semiconductor fabrication techniques.
Data Source
AI summary
Disclosed are forksheet (FS) cells whose shared gate and source/drains (S/Ds) are split by a dielectric wall. The cell include backside contacts—a backside gate strap contact, a backside passthrough contact, and direct backside contacts (BSCs). The backside contacts overcome the gate obstacle problem and the contact obstacle problem of conventional FS cells.