Forksheet BJT Nanosheet Layout for Tighter Transistor Spacing
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Solution Overview
Problem
Existing integrated circuit designs face challenges in reducing the minimum spacing between transistors, particularly in CMOS forksheet semiconductor structures, which limits size scaling and increases power consumption.
Innovation Solution
A semiconductor structure is developed with a dielectric body and transistors, including semiconductor nanosheets positioned laterally adjacent to the sidewalls, allowing for reduced spacing between bipolar junction transistors (BJTs) or between a BJT and a field effect transistor (FET), utilizing trench isolation regions and selectively grown semiconductor layers to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional CMOS forksheet semiconductor structure is used, then FET performance is achieved, but minimum spacing between transistors cannot be reduced further and power consumption increases
Solution Approach 1:
The patent transitions from planar transistor布局 to a three-dimensional forksheet structure where semiconductor nanosheets are positioned laterally adjacent to opposing sidewalls of a dielectric body. This vertical stacking and lateral positioning in multiple dimensions enables reduced spacing between transistors while maintaining electrical performance, directly resolving the contradiction between minimizing spacing and controlling power consumption.
Solution Approach 2:
The invention embeds semiconductor nanosheets within a dielectric body structure, where the nanosheets are nested laterally adjacent to the sidewalls. This nesting arrangement allows compact integration of multiple transistors in a shared dielectric body, reducing overall device footprint and spacing while maintaining individual transistor performance and power efficiency.
2Area of stationary object
If transistor spacing is reduced for size scaling, then device density improves, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric body serves as an intermediary structure that precisely positions and isolates the semiconductor nanosheets. By using the dielectric body as a template with defined sidewalls, the manufacturing process can control nanosheet positioning with high precision, enabling reduced spacing while maintaining manufacturing feasibility and consistent device density across production.
Solution Approach 2:
The invention segments the semiconductor structure into discrete nanosheets positioned at specific locations (laterally adjacent to opposing sidewalls) within the dielectric body. This segmentation allows independent optimization and precise control of each transistor's position and dimensions, facilitating high-precision manufacturing and consistent device density scaling.
3Power
If BJT is included for improved drive and analog function, then device performance improves, but device complexity increases
Solution Approach 1:
The forksheet semiconductor structure with laterally positioned nanosheets provides a universal platform that can accommodate both FET and BJT transistor types. By using the same dielectric body and nanosheet positioning approach for different transistor types, the invention achieves multi-functionality without proportionally increasing complexity, enabling enhanced drive capability and analog performance while maintaining manufacturing efficiency.
Data Source
AI summary
Disclosed are a forksheet semiconductor structure and a method of forming the structure. The structure can include a dielectric body with a first sidewall and a second sidewall opposite the first sidewall. The structure can include a first transistor, which incorporates first semiconductor nanosheet(s) positioned laterally immediately adjacent to the first sidewall of the dielectric body, and a second transistor, which incorporates second semiconductor nanosheet(s) positioned laterally immediately adjacent to the second sidewall. The first transistor and the second transistor can both be bipolar junction transistors (BJTs) (e.g., PNP-type BJTs, NPN-type BJTs or a PNP-type BJT and an NPN-type BJT). Alternatively, the first transistor can be a BJT (e.g., a PNP-type BJT or an NPN-type BJT) and the second transistor can be a field effect transistor (FET) (e.g., an N-type FET (NFET) or a P-type FET (PFET)).