Forksheet CMOS Layout for Arbitrary β Ratio Control
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Solution Overview
Problem
Current lithographic etching processes for forming forksheet transistors often result in misalignment, limiting the effective width ratio (β) of left and right portions to 1:1, which may not be desirable, and previous methods to avoid misalignment restrict β to this value.
Innovation Solution
A method involving etching a hardmask on a nanosheet stack to form hardmask caps with varying widths and spacings, depositing spacers, and reactive ion etching to create trenches of varying widths, followed by sacrificial liner deposition and etching to form dielectric pillars, allowing for arbitrary β between pFET and nFET portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lithographic etching process is used to form forksheets, then the process is simple and direct, but misalignment occurs causing β ratio to diverge from expected value
Solution Approach 1:
The patent applies preliminary action by forming spacers on the sides of hardmask columns before etching the nanosheet stack. This pre-formation of spacers establishes precise geometric constraints that guide the subsequent etching process, ensuring accurate β ratio control while maintaining process simplicity
Solution Approach 2:
The patent introduces spacers as an intermediary element between the hardmask columns and the nanosheet stack. These spacers act as a mediating structure that transfers the dimensional information from the hardmask to the final forksheet geometry, enabling precise β ratio control without direct lithographic patterning of the forksheets themselves
2Manufacturing precision
If spacers are grown on hardmask columns to avert misalignment, then β ratio control improves, but β is limited to 1:1
Solution Approach 1:
The patent applies local quality by making the spacers asymmetric in their formation or removal. Different regions of the structure receive different treatments - one side retains the spacer while the other side has it removed or modified, enabling arbitrary β ratios rather than being constrained to symmetric 1:1 configurations
Solution Approach 2:
The patent introduces asymmetry by selectively removing or modifying spacers on one side of the hardmask columns while preserving them on the other side. This asymmetric treatment of otherwise symmetric structures enables flexible β ratio control, allowing the effective widths of pFET and nFET portions to have arbitrary ratios
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of forksheet nanodevices with well-controlled spacing and arbitrary β between pFET and nFET portions, facilitating the creation of both forksheet and gate-all-around nanodevices with precise transistor arrays.
Implementation Method 1
isotropically etching back the sacrificial liner so that portions of the sacrificial liner are removed from trenches that are wider than twice the liner thickness, while other portions of the sacrificial liner remain in pinch-off trenches that are narrower than twice the liner thickness
Implementation Method 2
depositing spacers on the hardmask and reactive ion etching the spacers to form gaps that correspond to the spaces that were separating the hardmask caps
Data Source
AI summary
A semiconductor structure includes a common substrate; a first forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate and that has an nFET (n-doped Field Effect Transistor) and a pFET (p-doped Field Effect Transistor) and has a first β (effective width ratio) between the nFET and the pFET; and a second forksheet device that is adjacent to the first forksheet device on the common substrate and that has a second β between a second nFET and a second pFET. The second β is different than the first β by at least 5 percent. Another semiconductor structure includes a common substrate; a forksheet complementary metal oxide semiconductor (CMOS) device that is located on the common substrate; and a gate-all-around (GAA) nanosheet CMOS device that is located on the common substrate and is adjacent to the forksheet device.