Forksheet Semiconductor Structure for Dense CMOS Integration
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in improving processing and manufacturing efficiency as the scaling down of ICs increases complexity and costs, while maintaining the complexity of processing and manufacturing ICs.
Innovation Solution
The method involves forming a multi-layer stack with alternating semiconductor layers over a substrate, etching trenches to create fin structures, and using dielectric materials to form forksheet structures, which allows for the integration of n-type and p-type devices within the same structure, enhancing processing efficiency and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into multiple alternating layers of first and second semiconductor materials forming a multi-layer stack. This segmentation allows for the formation of complex three-dimensional device architectures (such as nanosheet transistors) while maintaining manufacturability through systematic layer-by-layer processing, thereby achieving high functional density without proportionally increasing processing complexity
Solution Approach 2:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by stacking multiple semiconductor layers vertically. This dimensional change enables increased functional density within the same chip area while using standard fabrication processes, thus improving productivity without requiring complex processing techniques
2Area of stationary object
If geometry size is decreased to increase functional density, then chip area utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor structure is divided into repeating units of alternating first and second semiconductor layers, creating a modular multi-layer stack. This segmentation enables scalable manufacturing where the same fabrication processes can be applied repeatedly to create complex three-dimensional device configurations, improving chip area utilization while keeping manufacturing complexity manageable
Solution Approach 2:
The patent varies the material composition parameters between alternating layers (different semiconductor materials with different properties) to create functionally distinct regions within the vertical stack. This parameter variation allows for the integration of n-type and p-type devices and formation of channel regions using standard epitaxial growth processes, enhancing manufacturing ease while maximizing chip area utilization
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain (S/D) region disposed over a substrate, a second S/D region disposed over the substrate, a dielectric wall disposed between the first and second S/D regions, a first conductive contact disposed over and electrically connected to the first S/D region, a second conductive contact disposed over and electrically connected to the second S/D region, and a first dielectric material in contact with the dielectric wall. The first dielectric material has a top surface located at a first level between a top surface of the first conductive contact and a bottom surface of the first conductive contact, and the first dielectric material extends from the first level to a second level located below the bottom surface of the first conductive contact.