Forksheet Gate Structure With Ferroelectric Layer for 3D Scaling
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in achieving high-density, three-dimensional (3D) integration due to limitations in scaling and device density, particularly at single-digit nanometer nodes.
Innovation Solution
The development of semiconductor devices with a forksheet structure, involving vertically stacked channel layers and a gate structure with a ferroelectric layer, allows for increased transistor density and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planar fabrication techniques are used to increase transistor density, then manufacturing precision can be maintained, but device density and scalability are limited at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from two-dimensional planar fabrication to three-dimensional vertical stacking by forming channel layers, gate structures, and isolation structures in multiple vertical levels. This dimensional change allows continued scaling and increased device density while maintaining manufacturing precision through adapted fabrication processes.
2Quantity of substance
If vertical stacking is implemented to increase 3D density, then device density improves, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: forming channel layers with first sacrificial layers, creating isolation structures, forming gate structures with second sacrificial layers, and selective removal of sacrificial layers. This segmentation manages complexity by breaking down the vertical stacking process into controllable, modular fabrication stages.
Solution Approach 2:
Sacrificial layers are pre-formed within the channel layers before the main device structure is completed. These preliminary structures guide subsequent fabrication steps and are selectively removed to create the final vertical transistor architecture, simplifying the overall process by preparing structures in advance.
3Quantity of substance
If scaling is continued in planar devices to reduce spacing, then transistor density increases, but scaling limitations are encountered at single-digit nanometer nodes
Solution Approach 1:
The patent resolves scaling limitations by moving from lateral planar scaling to vertical stacking, where transistors are arranged in multiple levels above the substrate. This allows continued increase in transistor density without further reduction in lateral spacing, overcoming the physical limits of single-digit nanometer planar scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher 3D density and improved performance by allowing for vertically stacked transistors and channels, overcoming scaling limitations in planar devices.
Implementation Method 1
The gate structure can include a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer
Data Source
AI summary
A semiconductor structure includes a stack of channel layers extending vertically over a substrate. The semiconductor structure includes a gate structure interleaved with the stack, where the gate structure wraps around a first end of each channel layer. The gate structure includes a dielectric layer over the channel layer, a ferroelectric layer over the dielectric layer, and a metal layer over the ferroelectric layer. The semiconductor structure includes an isolation structure disposed over a second end of each channel layer opposite the first end.