Forksheet FET Capacitive Cell Layout for Noise-Immune Chip Scaling
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Solution Overview
Problem
Recent advancements in semiconductor integrated circuits towards miniaturization and higher integration have led to increased noise and decreased noise immunity, causing circuit malfunctions, and there is a lack of examination on capacitive cells using forksheet FETs to address these issues.
Innovation Solution
A layout structure for a capacitive cell using forksheet FETs is provided, where p-type and n-type transistors are arranged with specific gate interconnects and pads to create capacitances, allowing for reduced spacing and increased capacitance area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet FETs are scaled down for miniaturization and higher integration, then device density and integration degree are improved, but noise increases and noise immunity decreases causing circuit malfunctions
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional nanosheet FETs with vertical channel structures. The nanosheets are stacked vertically and surrounded by gate electrodes on multiple sides, creating a 3D configuration that improves gate control and reduces off-current while maintaining small footprint. This dimensional change allows higher integration without proportionally increasing noise susceptibility.
Solution Approach 2:
The patent implements a nested structure where multiple nanosheets are stacked vertically within a compact footprint, and gate electrodes surround the nanosheets from multiple directions. The forksheet FET configuration nests the channel-forming nanosheets within a gate structure that envelops them, achieving high device density while maintaining reliable electrical characteristics through improved gate control.
2Reliability
If decoupling capacitance is added to prevent noise-caused circuit malfunctions, then noise immunity is improved, but device area increases
Solution Approach 1:
The patent combines the decoupling capacitance function with the existing transistor structure by utilizing the gate electrodes and nanosheet configurations to provide capacitive effects. The forksheet FET structure and surrounding gate interconnects serve dual purposes: controlling the nanosheet channels and providing decoupling capacitance to suppress noise, thereby eliminating the need for separate capacitance elements and reducing overall cell area.
Solution Approach 2:
The gate electrodes and interconnect structures in the nanosheet FET configuration perform multiple functions simultaneously: they control the channel formation in nanosheets, provide electrical connections, and serve as decoupling capacitance elements. This multi-functionality allows the same structural elements to address both transistor operation and noise immunity requirements without increasing device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This layout structure enables the implementation of a large-capacity capacitive cell using forksheet FETs, which can help in downsizing and increasing the integration of semiconductor chips while reducing noise-related malfunctions.
Implementation Method 1
the first pair of pads and the second gate interconnect are supplied with a first power supply voltage, and the second pair of pads and the first gate interconnect are supplied with a second power supply voltage lower than the first power supply voltage
Data Source
AI summary
A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.