Forksheet FET Capacitive Cell Layout for On-Chip Noise Mitigation
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Solution Overview
Problem
Recent semiconductor integrated circuits face challenges with increased noise due to miniaturization and higher integration, leading to circuit malfunctions, and there is a need for effective decoupling capacitance methods, particularly for nanosheet (nanowire) FETs, which have not been adequately addressed.
Innovation Solution
A layout structure for a capacitive cell using forksheet FETs is implemented, with specific configurations of nanosheet units, gate interconnects, and power supply voltages to create capacitances between nanosheets and interconnects, reducing spacing and enhancing capacitance area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet FETs are used for further miniaturization and higher integration, then device integration density is improved, but noise increases causing circuit malfunctions
Solution Approach 1:
The patent introduces decoupling capacitance as an intermediary element between power supply nodes to filter noise. The capacitance acts as a mediator that absorbs high-frequency noise generated by rapid switching in highly integrated nanosheet FET circuits, preventing noise from causing circuit malfunctions while maintaining high integration density.
Solution Approach 2:
The patent changes the electrical parameters of the circuit by introducing capacitive elements with specific capacitance values. This parameter change allows the circuit to maintain stability and noise immunity despite the increased integration density and associated noise generation from nanosheet FETs.
2Reliability
If decoupling capacitance is provided between power supplies to prevent noise-caused malfunctions, then noise immunity is improved, but device area increases
Solution Approach 1:
The patent merges the decoupling capacitance function with existing circuit structures such as gate interconnects and power supply lines. By combining multiple functions into single structural elements, the patent achieves noise filtering without proportionally increasing device area, as the same structures serve both signal transmission and decoupling purposes.
Solution Approach 2:
The patent designs circuit elements to perform multiple functions simultaneously. For example, gate interconnects serve both as signal routing pathways and as decoupling capacitance elements. This multi-functionality reduces the need for dedicated noise-filtering structures, thereby limiting area expansion while improving noise immunity.
3Reliability
If capacitance is increased to reduce noise, then noise immunity is improved, but capacitance area efficiency decreases
Solution Approach 1:
The patent transitions from planar capacitance structures to three-dimensional configurations. By stacking nanosheet FETs and positioning decoupling capacitance elements in vertical dimensions rather than only horizontal plane, the patent achieves higher capacitance values without proportionally increasing the footprint area, thereby improving capacitance area efficiency.
Solution Approach 2:
The patent nests decoupling capacitance structures within existing circuit geometries. Capacitance-forming elements are positioned within the vertical and horizontal spaces already occupied by transistor stacks and interconnect layers, utilizing unused volume to provide decoupling functionality without expanding the overall device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of a large-capacity capacitive cell using forksheet FETs, effectively reducing the area of the capacitive cell and securing larger capacitances, which helps in mitigating noise-related issues and improving semiconductor chip integration and downsizing.
Implementation Method 1
a first gate interconnect extending in the first direction, formed to surround a periphery of the nanosheet of the first nanosheet unit in the first direction and a third direction perpendicular to the first and second directions
Data Source
AI summary
A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads 22c, 22d and a gate interconnect 36c, and VSS is supplied to a pair of pads 27c, 27d and a gate interconnect 31c. Capacitances are produced between nanosheets 21c and the gate interconnect 31c and between nanosheets 26c and the gate interconnect 36c. The faces of the nanosheets 21c closer to the nanosheets 26c are exposed from the gate interconnect 31c, and the faces of the nanosheets 26c closer to the nanosheets 21c are exposed from the gate interconnect 36c.