Forksheet FET Capacitor Layout for High Breakdown Voltage
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Solution Overview
Problem
Semiconductor integrated circuit devices face challenges with low breakdown voltage and increased power consumption due to excessive transistor scaling, particularly in interfaces requiring high voltages, and there is a lack of effective layout structures for high-breakdown voltage capacitive elements using forksheet FETs.
Innovation Solution
A capacitive element layout is designed using forksheet FETs, where transistors with nanosheets are arranged to minimize the distance between gate interconnects, allowing for a reduced size while maintaining high breakdown voltage, achieved by exposing faces of nanosheets from gate interconnects to facilitate adjacent transistor connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor scaling is performed to improve integration degree and operating speed, then integration degree and operating speed are improved, but off current increases and power consumption increases
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional nanosheet FETs with fork-shaped gate electrodes. The nanosheet channel extends in the vertical dimension, and the gate electrode wraps around the nanosheet in a three-dimensional configuration, enabling better gate control and reduced off-current while maintaining small footprint for high integration density
2Productivity
If transistor scaling is performed to improve integration degree and operating speed, then integration degree and operating speed are improved, but breakdown voltage decreases
Solution Approach 1:
The three-dimensional nanosheet structure with fork-shaped gate provides superior electrostatic control compared to planar devices. The gate electrode wraps around the nanosheet channel in multiple directions, enabling effective control of the channel even at scaled dimensions, thereby maintaining adequate breakdown voltage while achieving high integration density
Solution Approach 2:
The fork-shaped gate electrode provides enhanced local control at critical regions of the nanosheet channel. The gate structure extends to wrap around portions of the nanosheet, creating localized electric field control that improves voltage breakdown characteristics at the transistor level while maintaining overall device scaling
3Ease of manufacture
If conventional planar transistors are used for capacitive elements, then manufacturing is simple, but area efficiency is poor and breakdown voltage is limited
Solution Approach 1:
The patent employs three-dimensional nanosheet FETs with fork-shaped gates to form capacitive elements. The vertical nanosheet structure and wrapped gate configuration enable the capacitive element to achieve high breakdown voltage and compact footprint, improving area efficiency while maintaining compatibility with existing nanosheet fabrication processes
Data Source
AI summary
A layout structure of a capacitive element using forksheet FETs is provided. A capacitive structure constituting the capacitive element includes: a first transistor having a first nanosheet extending in the X direction and a first gate interconnect extending in the Y direction and surrounding the periphery of the first nanosheet; and a second transistor having a second nanosheet extending in the X direction and a second gate interconnect extending in the Y direction and surrounding the periphery of the second nanosheet. The face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and the face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.