Forksheet FET Conductive Wall for Threshold-Voltage Control
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Solution Overview
Problem
Existing transistor structures face challenges in achieving high transistor density and effective threshold-voltage control, particularly in multi-bridge channel field-effect transistors and nanosheet FETs, where conventional dielectric walls limit further scaling and integration of complementary metal-oxide-semiconductor (CMOS) ICs.
Innovation Solution
The introduction of a conductive wall within the gate structure of forksheet transistors, which is distinct from the main gate structure, allows for additional threshold-voltage control and enables the same type of transistors (e.g., both PMOS or NMOS) to be placed on opposite sides, combined with a stacked transistor structure to enhance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dielectric walls are used to separate transistors, then transistor isolation is achieved, but threshold-voltage control is limited and transistor density cannot be further scaled
Solution Approach 1:
The patent changes the material parameter of the wall from dielectric (insulating) to conductive, enabling electrical control of threshold voltage. The conductive wall material is selected to have appropriate work function to modulate the threshold voltage of adjacent transistors, thereby achieving precise control over device electrical characteristics while maintaining structural simplicity.
Solution Approach 2:
The conductive wall serves multiple functions simultaneously: it acts as a separator between adjacent transistors, provides threshold-voltage control through its work function, and enables independent control of each transistor in the forksheet structure. This multi-functionality resolves the contradiction by achieving enhanced control without proportionally increasing structural complexity.
2Quantity of substance
If more transistors are integrated in IC devices, then transistor density increases, but device area becomes constrained
Solution Approach 1:
The patent transitions from conventional planar transistor arrangements to a three-dimensional forksheet structure where transistors are stacked vertically and separated by conductive walls. This dimensional change allows multiple transistors to occupy a smaller footprint area by utilizing the vertical dimension, thereby increasing transistor density without proportionally increasing the IC device area.
Solution Approach 2:
The forksheet transistor structure nests multiple transistors within a compact configuration, with conductive walls positioned between adjacent transistors. This nested arrangement allows efficient packing of transistors in the available space, maximizing the quantity of transistors that can be integrated into a given device area.
3Quantity of substance
If forksheet transistor structure is implemented, then transistor density increases, but threshold-voltage control becomes challenging
Solution Approach 1:
The conductive wall material is specifically selected with appropriate work function parameters to enable threshold-voltage control in the forksheet structure. By adjusting the work function of the conductive wall material, precise control over the threshold voltage of adjacent transistors is achieved, resolving the control challenges introduced by the high-density forksheet configuration.
Data Source
AI summary
Forksheet field-effect transistor (FET) devices are provided. A forksheet FET device includes a first FET having a first conductive gate material. The forksheet FET device includes a second FET that is adjacent the first FET and that has the first conductive gate material. Moreover, the forksheet FET device includes a conductive wall that separates the first FET from the second FET. The conductive wall includes a second conductive gate material that is different from the first conductive gate material.