Forksheet FET Structure With Gate-All-Around Nanosheet Coverage
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Solution Overview
Problem
Forksheet field-effect transistors (FETs) face performance losses due to short-channel effects and inability to achieve a gate-all-around design, limiting further scaling and optimization.
Innovation Solution
A method for producing a FET structure with a forksheet nanosheet design, involving the generation of a first structure with alternating material layers and a dielectric wall, followed by cavity creation and isotropic etching to recess the wall, allowing complete gate dielectric and metal coverage around the nanosheet channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a dielectric isolation wall is used in forksheet FET to separate pMOS and nMOS, then area scaling is improved, but gate-all-around design becomes impossible
Solution Approach 1:
The device is segmented into first and second layer stacks separated by a dielectric wall, with selective material removal in each stack to create independent cavities. This segmentation allows the gate to wrap around nanosheets in each stack independently, achieving gate-all-around coverage while maintaining the area benefits of the forksheet configuration with the dielectric wall.
Solution Approach 2:
The gate structure extends into the vertical dimension by wrapping around the nanosheets in a three-dimensional configuration. The gate dielectric and gate metal layers are deposited to completely surround the nanosheet channels on all four sides, transitioning from a planar gate to a vertical gate-all-around structure that overcomes the limitation of the dielectric wall.
2Ease of manufacture
If conventional planar MOSFET gate design is used, then manufacturing is simpler, but scalability is limited
Solution Approach 1:
The gate structure is nested around the nanosheet channels in a concentric configuration, with the gate dielectric layer surrounding the nanosheets and the gate metal layer surrounding the dielectric. This nested gate-all-around structure provides superior scalability compared to planar gates while maintaining manufacturability through sequential deposition processes.
3Reliability
If gate-all-around design is implemented in forksheet FET, then short-channel effects are reduced, but dielectric isolation prevents complete gate coverage
Solution Approach 1:
The device is segmented into first and second layer stacks separated by a dielectric wall, with selective material removal in each stack to create independent cavities. This segmentation allows the gate to wrap around nanosheets in each stack independently, achieving gate-all-around coverage while maintaining the area benefits of the forksheet configuration with the dielectric wall.
Solution Approach 2:
The gate structure extends into the vertical dimension by wrapping around the nanosheets in a three-dimensional configuration. The gate dielectric and gate metal layers are deposited to completely surround the nanosheet channels on all four sides, transitioning from a planar gate to a vertical gate-all-around structure that overcomes the limitation of the dielectric wall.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables a gate-all-around design in FET structures, reducing performance losses and allowing for further scaling and optimization, while maintaining effective gate coverage on all sides.
Implementation Method 1
etching into one side of the wall through the one or more cavities in the first layer stack to recess the side of the wall
Data Source
AI summary
The present disclosure relates to a method for producing a field-effect transistor, FET, structure (10, 10′, 10″, 10′″). The method comprises the steps of: a) generating a first structure on a substrate (11), the first structure comprising a first layer stack (12a), a second layer stack (12b), and a wall (15) between the first layer stack (12a) and the second layer stack (12b), wherein the first layer stack (12a) and the second layer stack (12b) each comprise one or more first material layers (13) and two or more second material layers (14) stacked in alternating manner, and wherein the wall (15) is electrically non-conductive; b) removing the one or more first material layers (13) of the first layer stack (12a) to generate one or more cavities in the first layer stack (12a); c) etching into one side of the wall (15) through the one or more cavities in the first layer stack (12a) to recess the side of the wall (15), thereby generating a vertical cavity (19) between the first layer stack (12a) and the recessed side of the wall (15); and d) filling the cavities in the first layer stack (12a) and the vertical cavity (19) with gate dielectric materials and gate metals (17).