Forksheet FET Isolation Wall for Threshold Voltage Uniformity
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits (ICs) has increased complexity and challenges in maintaining uniform active area spacing, symmetrical source/drain epitaxy structures, and reduced metal gate endcap, leading to increased gate-drain capacitance and high threshold voltage variation.
Innovation Solution
A self-aligned gate isolation wall is formed in a replacement gate process, confined between sidewall spacers and active areas, using a high-k gate dielectric to reduce cell height and capacitance, and a forksheet structure is implemented to enhance gate control and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases and uniformity of active area spacing becomes difficult to maintain
Solution Approach 1:
The patent applies preliminary action by forming the gate isolation wall structure before the final gate electrode deposition. The gate isolation wall is formed as a self-aligned structure using sidewall spacers as masks, which pre-establishes the isolation regions and simplifies subsequent processing steps. This preliminary structuring enables better control over active area spacing at scaled dimensions.
Solution Approach 2:
The patent segments the gate structure into multiple components: the gate electrode, the gate isolation wall, and sidewall spacers. This segmentation allows each component to be optimized independently - the gate isolation wall provides electrical isolation while the gate electrode provides control functionality. The segmented structure also enables self-alignment through the sidewall spacer masking process.
2Quantity of substance
If geometry size is decreased to increase functional density, then more devices fit per chip area, but uniform active area spacing and symmetrical source/drain epitaxy structures become difficult to maintain
Solution Approach 1:
The patent employs self-service through self-aligned fabrication processes. The sidewall spacers automatically form at precise locations relative to the active areas, and the gate isolation wall forms conformally between these spacers. This self-alignment mechanism ensures uniform active area spacing without requiring additional lithography alignment steps, maintaining manufacturing precision at scaled dimensions.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming the gate isolation wall as a three-dimensional structure that extends between active areas. This vertical isolation structure effectively separates adjacent devices in the vertical space, enabling better control over spacing uniformity without increasing lateral complexity.
3Reliability
If metal gate endcap is reduced to improve device performance, then gate control is enhanced, but gate-drain capacitance increases
Solution Approach 1:
The patent extracts the isolation function from the main gate electrode structure by introducing a separate gate isolation wall structure. This allows the gate electrode endcap to be minimized for better gate control while the gate isolation wall provides the necessary electrical isolation, preventing excessive gate-drain capacitance. The harmful capacitance effect is isolated to specific regions controlled by the gate isolation wall.
4Volume of moving object
If cell height is reduced to improve device density, then functional density increases, but capacitance management becomes more challenging
Solution Approach 1:
The patent applies local quality by positioning the gate isolation wall specifically at regions where capacitance management is critical - between active areas and near the gate electrode ends. The gate isolation wall provides localized electrical isolation that reduces parasitic capacitance in key areas while allowing the overall cell height to be minimized for high density. Different regions of the device have different isolation characteristics optimized for their specific functions.
Data Source
AI summary
A device includes: a first stack of nanostructures; a second stack of nanostructures horizontally offset from the first stack; a first source/drain region abutting the first stack of nanostructures; a second source/drain region abutting the second stack of nanostructures; a wall structure between the first and second stacks and spaced apart from the nanostructures of the first stack; and a first gate structure, which includes: a gate dielectric layer that wraps around the nanostructures of the first stack; and a conductive core layer on the gate dielectric layer, wherein thickness of the conductive core layer between one of the nanostructure of the first stack and the wall structure is in a range of 0 nanometers to 1 nanometer, inclusive.