Forksheet Transistor Gate Cut Layout With Early Isolation Formation
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Solution Overview
Problem
The challenge in manufacturing semiconductor devices with forksheet transistors lies in the difficulty of forming a gate cut structure after the gate structure is formed, which requires precise high-aspect ratio etching and complicates the manufacturing process.
Innovation Solution
The gate cut structure is formed simultaneously with the isolation wall during the initial stages of manufacturing, avoiding the need for precise patterning and simplifying the process, thereby improving production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate cut structure is formed after the gate structure is formed, then the device structure can be precisely defined, but the manufacturing process becomes complex and difficult
Solution Approach 1:
The gate cut structure is formed in advance during the isolation wall formation process, before the gate structure is created. This preliminary action eliminates the need for subsequent complex high-aspect ratio etching operations, thereby reducing manufacturing process complexity while maintaining the necessary structural precision through controlled formation steps
2Ease of manufacture
If the gate cut structure is formed simultaneously with the isolation wall, then the manufacturing process is simplified, but the precision of the gate cut structure may be compromised
Solution Approach 1:
The formation of the gate cut structure is merged with the isolation wall formation process into a single integrated step. This combining of operations simplifies the manufacturing process by eliminating separate patterning and etching steps, while the precision requirements are met through the controlled deposition and patterning of the isolation wall material that simultaneously defines both the isolation structure and the gate cut geometry
3Manufacturing precision
If high-aspect ratio etching is used to form the gate cut structure, then the structural precision is improved, but the production yield decreases
Solution Approach 1:
The gate cut structure is created in advance during the isolation wall formation process, avoiding the need for subsequent high-aspect ratio etching operations. This preliminary formation approach maintains structural precision through controlled deposition processes while significantly improving production yield by eliminating complex and yield-limiting etching steps
Data Source
AI summary
Provided is a semiconductor device which includes: a 1st transistor including a 1st channel structure and a 1st gate structure on the 1st channel structure; a 2nd transistor including a 2nd channel structure and a 2nd gate structure on the 2nd channel structure; a 3rd transistor including a 3rd channel structure and a 3rd gate structure on the 3rd channel structure; an isolation wall between the 1st channel structure and the 2nd channel structure; a gate cut structure between the 1st gate structure and the 2nd gate structure; and a 1st active isolation structure between the 1st channel structure and the 3rd channel structure, below a level of a bottom surface of the 1st channel structure or the 3rd channel structure, wherein the gate cut structure penetrates the 1st active isolation structure through a bottom surface thereof.