Forksheet Gate Cut Spine Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The formation of semiconductor devices with densely packed transistors poses challenges in isolating adjacent transistors due to the difficulty in forming dielectric spines that can withstand aggressive etch processes, leading to undesirably high parasitic capacitance from using high-k dielectric materials.
Innovation Solution
Forming a dielectric spine as a gate cut that passes through both the metal gate and nanoribbons or nanosheets after the formation of the gate structures, allowing the use of low-k dielectric materials to reduce parasitic capacitance, and forming the dielectric spine via lithographic alignment which can result in asymmetrical nanoribbon widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials are used for the dielectric spine to withstand aggressive etch processes, then the structural integrity and etch resistance are improved, but the parasitic capacitance increases
Solution Approach 1:
The gate structure is formed first, and then the dielectric spine is formed by depositing low-k dielectric material and performing a second etch process. This preliminary formation of the gate structure allows the use of low-k materials that would otherwise be damaged by aggressive etching, since the gate structure protects the dielectric material during the etch process.
Solution Approach 2:
The patent changes the dielectric constant parameter of the spine material from high-k to low-k. This parameter change reduces parasitic capacitance while the process sequence (forming gate structure first, then dielectric spine) ensures the low-k material can withstand the etch conditions through the protective gate structure.
2Area of stationary object
If transistors are packed more densely to reduce device size, then the area is reduced, but the difficulty of forming isolation structures increases
Solution Approach 1:
The patent merges the gate cut function with the dielectric spine function. The same low-k dielectric material and etch process that create the dielectric spine for electrical isolation also create the gate cut for gate electrode definition. This consolidation of functions simplifies the manufacturing process while enabling dense transistor packing.
Solution Approach 2:
The dielectric spine serves multiple functions: it provides electrical isolation between adjacent transistors, acts as a structural support, and defines the gate cut position. This multi-functionality reduces the number of separate structures needed, simplifying the overall device architecture and easing manufacturing.
3Ease of manufacture
If lithographic alignment is used to form the dielectric spine, then the manufacturing process is simplified, but asymmetrical nanoribbon widths may result
Solution Approach 1:
The patent changes the tolerance parameter for nanoribbon width symmetry. By accepting asymmetrical widths as a valid parameter variation rather than a defect, the patent enables the use of simpler lithographic alignment processes without compromising device functionality, since the low-k dielectric spine maintains electrical isolation effectiveness regardless of minor width variations.
Data Source
AI summary
Techniques are provided to form semiconductor devices that include a gate cut that passes through a plurality of semiconductor bodies (e.g., nanoribbons or nanosheets) such that the gate cut acts as a dielectric spine in a forksheet arrangement with the semiconductor bodies on either side of the gate cut. In an example, two semiconductor devices in a forksheet arrangement include semiconductor bodies directly on either side of a dielectric spine. A gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) that extends around each of the semiconductor bodies of both semiconductor devices. The dielectric spine interrupts the entire height of the gate structure between the two devices and includes dielectric material (e.g., low-k dielectric), and the gate dielectric of the gate structure is not present along sidewalls of the spine between adjacent bodies.