Forksheet Gate Isolation Using Wide Gate Cut Structures
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Solution Overview
Problem
The existing manufacturing process of forksheet transistors faces challenges in achieving sufficient isolation between gate structures due to misalignment and insufficient height of isolation walls, leading to potential connectivity issues and functional failures in semiconductor devices.
Innovation Solution
The implementation of wide gate cut structures on isolation walls, with increased width and alignment margins, ensures effective isolation between gate structures, addressing misalignment issues and enhancing manufacturing simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional isolation walls are used in forksheet transistor manufacturing, then the manufacturing process is simpler, but the isolation between gate structures is insufficient leading to misalignment issues
Solution Approach 1:
The isolation structure is segmented into two distinct components: the isolation wall that provides vertical separation between adjacent transistors, and the gate cut structure that provides horizontal isolation between gate structures. This segmentation allows each component to be optimized independently - the isolation wall for vertical isolation and the gate cut structure for horizontal alignment tolerance, thereby resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
The gate cut structure acts as an intermediary element between the isolation wall and the gate structures. It provides an additional isolation layer that mediates the alignment between adjacent gate structures, compensating for manufacturing variations and ensuring sufficient isolation without requiring extremely precise alignment of the isolation wall itself.
2Reliability
If isolation wall height is increased to improve isolation, then misalignment is reduced, but manufacturing complexity and difficulty increase
Solution Approach 1:
The isolation function is segmented between the isolation wall and the gate cut structure. The isolation wall provides the primary vertical isolation, while the gate cut structure provides additional horizontal isolation. This segmentation allows the isolation wall to maintain a manageable height that is easier to manufacture, while the gate cut structure supplements the isolation effectiveness, thereby resolving the contradiction between reliability and ease of manufacture.
Solution Approach 2:
Instead of making the isolation wall excessively tall to achieve sufficient isolation, the solution uses partial action by adding the gate cut structure as a supplementary isolation element. This approach achieves the required isolation effectiveness without the manufacturing difficulties associated with creating extremely tall isolation walls.
3Manufacturing precision
If gate cut structure width is increased to improve alignment margins, then manufacturing reliability improves, but device area increases
Solution Approach 1:
The gate cut structure is positioned locally at the critical interface between adjacent transistors where alignment precision is most needed. By concentrating the alignment margin provision at this specific location rather than uniformly across the entire device, the solution achieves improved manufacturing precision without proportionally increasing the overall device area.
Solution Approach 2:
The gate cut structure provides partial compensation for alignment variations through its width, which is designed to be sufficient for manufacturing tolerances but not excessively large. This partial action approach achieves the necessary alignment margin while minimizing the area overhead, resolving the contradiction between manufacturing precision and device area.
Data Source
AI summary
Provided is a semiconductor device which includes: a 1st transistor including a 1st channel structure extended in a 1st direction, and a 1st gate structure on the 1st channel structure; a 2nd transistor comprising a 2nd channel structure extended in the 1st direction, and a 2nd gate structure on the 2nd channel structure, the 2nd transistor being disposed adjacent to the 1st transistor in a 2nd direction that horizontally intersects the 1st direction; a 1st isolation wall between the 1st channel structure and the 2nd channel structure; and a 1st gate cut structure between the 1st gate structure and the 2nd gate structure on the 1st isolation wall in a 3rd direction that vertically intersects the 1st direction and the 2nd direction.