Forksheet Nanosheet Gate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Nanosheet devices face issues with interference and difficulty in forming connections to a backside power network as they scale down, leading to parasitic capacitance and degraded performance.
Innovation Solution
A semiconductor device structure is developed with a backbone pattern, sacrificial nanosheets removal, and a work function metal wrapping around nanosheets, along with a minimum gate metal design to minimize parasitic capacitance, involving stages of dielectric formation, work function metal deposition, and conductive metal fill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet devices are scaled down to increase density, then device integration is improved, but parasitic capacitance increases and device performance degrades
Solution Approach 1:
The patent extracts and removes the gate extension structure from conventional designs, keeping only the minimum necessary gate metal directly over the nanosheets. This extraction eliminates the harmful parasitic capacitance associated with extended gate regions while preserving the essential gate function for controlling the nanosheet channels.
Solution Approach 2:
The gate structure is segmented into discrete regions: gate metal directly over each nanosheet, separated by dielectric material. This segmentation isolates the gate regions from each other, reducing inter-gate parasitic capacitance and allowing independent control of adjacent nanosheet devices.
2Device complexity
If conventional gate metal design is used, then gate control is simplified, but parasitic capacitance increases
Solution Approach 1:
The gate extension portion is extracted and removed from the structure. Only the minimum gate metal necessary for direct control of the nanosheet is retained, positioned precisely over the nanosheet width. This eliminates the parasitic capacitance contribution from extended gate regions while maintaining essential gate functionality.
3Ease of operation
If connections to backside power network are formed at scale, then device connectivity is improved, but manufacturing difficulty increases
Solution Approach 1:
Dielectric bars are formed preliminarily during the nanosheet fabrication process, extending through the nanosheets to the substrate. These bars are prepared in advance with appropriate openings and interfaces, enabling straightforward formation of through-substrate connections to the backside power network without complex subsequent manufacturing steps.
Data Source
AI summary
According to an embodiment of the present invention, a semiconductor device includes a substrate. A plurality of nanosheets are located parallel to the substrate. A first dielectric bar extends upwards from the substrate through the plurality of nanosheets. The plurality of nanosheets extend laterally from sidewalls of the first dielectric bar. A high-k dielectric metal on a frontside surface and a backside surface of each nanosheet in the plurality of nanosheets and on the sidewalls of the first dielectric bar. A work function metal on a frontside surface, a backside surface, and exposed sidewalls of the high-k dielectric metal. A conductive metal fill between the work function metal. The conductive metal fill connecting to a sidewall of the work function metal.